Patents by Inventor Tetsuya Ueda

Tetsuya Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5760429
    Abstract: An integrated circuit having a multi-layered metal wiring structure with interlayer insulating films therebetween. A small cutout is made in a metal wiring when it is desirous to have the metal wiring touch a contact formed in a through hole passing through said cutout. A larger cutout is made in a metal wiring when it is desirous to have the metal wiring remain spaced from a contact formed in a through hole passing through said cutout.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: June 2, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kousaku Yano, Tetsuya Ueda
  • Patent number: 5733812
    Abstract: There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed.
    Type: Grant
    Filed: December 12, 1995
    Date of Patent: March 31, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuya Ueda, Takashi Uehara, Kousaku Yano, Satoshi Ueda
  • Patent number: 5701033
    Abstract: A semiconductor device comprising a substrate having a hollow cavity for mounting a semiconductor element therein and a lowered step surface at a periphery of the cavity for mounting a chip component thereon. A semiconductor element is mounted within the cavity and a chip capacitor is mounted to the lowered step surface. The semiconductor element and the chip component are adapted to be connected to an external circuit through electrical conductors. A cap is attached to the substrate and a seal material is filled into a space defined between the cap and the substrate for sealing the cavity and for encapsulating the chip component on the lowered step surface which may extend along the entire periphery of the cavity. The cap may include a projection adapted to abut gainst a side wall of the lowered step surface, or alternatively, the lowered step surface may include a side wall having a projection adapted to abut against periphery of the cap.
    Type: Grant
    Filed: January 30, 1996
    Date of Patent: December 23, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Jun Shibata, Yomiyuki Yama
  • Patent number: 5603742
    Abstract: A dust removing apparatus includes a filter and mounting frame which prevent leakage of dirty gas and improve the collection factor of soot dust even if dirty gas of a high temperature is subjected to a dust removing operation. The apparatus includes a filter element held in a filter element mounting frame, wherein a flange is disposed on an end of the filter element located on the side which receives dirty gas, and wherein the side of the flange opposite the dirty gas side is pressed against a flange of the filter element mounting frame. A seal packing is disposed between the filter flange and frame flange to seal the elements. Further, a plurality of honeycomb filter elements structured as above may be collected and accommodated to form a honeycomb pack.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: February 18, 1997
    Assignees: Mitsubishi Jukogyo Kabushiki Kaisha, NGK Insulators, Ltd.
    Inventors: Kiyoshi Nagashima, Tetsuya Ueda, Hisataka Urakata, Tetsuya Fujino, Yuichiro Kitagawa, Satoshi Uchida, Yasuo Akitu, Yosiaki Hori
  • Patent number: 5592019
    Abstract: A semiconductor device in a vertical surface mount package, reduced in size and having a higher heat radiating capacity, a method of producing the semiconductor device, and a semiconductor module. Leads of a first lead frame and leads of a second lead frame are parallel to each other and at least a portion of the leads overlap leads of the other lead frame when geometrically projected on them. An inner lead may extend out from the semiconductor package or the back side of a die pad in the semiconductor package may be exposed. The invention allows more outer leads to be used and makes it possible to reduce the size of the semiconductor device and to achieve high density mounting.
    Type: Grant
    Filed: April 4, 1995
    Date of Patent: January 7, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Kisamitsu Ono, Kou Shimomura, Hideyuki Ichiyama
  • Patent number: 5576247
    Abstract: A BPSG layer serving as a silicon oxide layer is formed on a semiconductor substrate 1. Formed on the surface of the BPSG layer is a hydrophobic molecular layer comprising hydrophobic groups such as methyl, ethyl and the like, by a silylation reaction (in which silyl having hydrophobic groups such as methyl groups, ethyl groups and the like, is reacted with OH groups, and in which the hydrophobic groups are substituted with H of the OH groups to generate --O--Si(CH.sub.3).sub.3 or the like). The molecular layer prevents the BPSG layer from absorbing moisture.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: November 19, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kousaku Yano, Masayuki Endo, Yuka Terai, Noboru Nomura, Tomoyasu Murakami, Tetsuya Ueda, Satoshi Ueda
  • Patent number: 5545919
    Abstract: Metal wires are formed side by side over a semiconductor substrate, with an interlayer insulating film interposed between the metal interconnections and the semiconductor substrate. The metal interconnections are covered with a passivation film composed of a lower silicon oxide film and an upper silicon nitride film. The silicon oxide film is deposited so that the maximum thickness of the portions of the silicon oxide film on the side faces of the metal interconnections is less than half of the minimum space between the metal interconnections. The silicon nitride film is deposited so as to be interposed between the portions of the silicon oxide film on the side faces of the adjacent metal interconnections.
    Type: Grant
    Filed: July 3, 1995
    Date of Patent: August 13, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Ueda, Tetsuya Ueda, Atsuhiro Yamano, Kousaku Yano
  • Patent number: 5518513
    Abstract: A dust removing apparatus suppresses pressure and temperature variations of cleaned gas to facilitate the removal of dust. A clean gas chamber delimited by a plurality of porous ceramic tubular filter elements is divided in two by a partition wall. The respective chambers are connected through discrete outlet pipes to a clean gas main pipe, and backwashing devices are provided in the respective outlet pipes. Furthermore, a porous ceramics filter element is provided on a bottom partition plate so that the gas flow velocity in the tubular filter elements can be insured to prevent dust from adhering thereto.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: May 21, 1996
    Assignee: Mitsubishi Jukogyo Kabushiki Kaisha
    Inventors: Atsumasa Iwanaga, Kiyoshi Nagashima, Tetsuya Ueda, Hisataka Urakata, Tetsuya Fujino
  • Patent number: 5508232
    Abstract: In a method of manufacturing a semiconductor device, overlaid on a first lead frame including a die pad supported by a plurality of die pad suspending leads is a second lead frame having connecting leads wherein the first and second lead frames are disposed on a first molding die such that the die pad and inner lead portions of the inner leads of the second lead frame are accommodated within a first cavity of the first molding die while offset portions of the die pad suspending leads are disposed outside of the first cavity. A second molding die is clamped onto the first molding die to define a resin molding chamber which is then filled with a molten resin to form a package. After removing the package from the first and second molding dies, the offset portions are cut away from the package while cutting the connecting leads to a predetermined length.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: April 16, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Kazunari Michii, Yutaka Koyama, Naoto Ueda
  • Patent number: 5385867
    Abstract: After accumulating a BPSG film layer on a silicon substrate, a first Al--Si--Cu film layer, a W film layer and a second Al--Si--Cu film layer are successively accumulated on this BPSG film layer. A resist pattern with wide-width and narrow-width pattern portions is formed on the second Al--Si--Cu film layer. The wide-width pattern portion is provided at a position corresponding to a contact for connecting a first-layer metallic wiring and a second-layer metallic wiring, while the narrow-width pattern portion is provided at a position corresponding to a wiring portion for the first-layer metallic wiring. After applying first etching on the second Al--Si--Cu film layer with a mask of the resist patter, second etching is applied on the W film layer. Thereafter, by applying third etching, the resist pattern remaining on the first-layer metallic wiring is removed and the first Al--Si--Cu film layer is transfigured into a tall metallic film portion and a short metallic film portion.
    Type: Grant
    Filed: March 24, 1994
    Date of Patent: January 31, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuya Ueda, Kousaku Yano, Tomoyasu Murakami, Michinari Yamanaka, Shuji Hirao, Noboru Nomura
  • Patent number: 5334872
    Abstract: A packaged semiconductor device includes a semiconductor chip having first and second surfaces, a plurality of electrodes formed on the first surface of the semiconductor chip, a die pad bonded to the second surface of the semiconductor chip for supporting the semiconductor chip, a plurality of leads having first and second ends, the first ends being connected to corresponding electrodes of the semiconductor chip, a heat spreading plate disposed in opposed relation to the die pad and having an area larger than that of the die pad, at least one end portion of the heat spreading plate lying in the same plane as the second ends of the plurality of leads, and a resin package body encapsulating the semiconductor chip, the die pad, the first ends of the plurality of leads, and the heat spreading plate.
    Type: Grant
    Filed: May 18, 1993
    Date of Patent: August 2, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Osamu Nakagawa
  • Patent number: 5327012
    Abstract: A semiconductor device having a double-layer interconnection with contact portions between first and second metal films, each having a multi-layered structure, covered with at least a silicon nitride film is provided wherein an electromigration characteristic at the contact portions is improved. The improvement is achieved by defining a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at the contact portions is not larger than 2/5 of a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at non-contact portions. By this, the stress exerted on the second metal film is reduced to improve the electromigration life at the contact portions by about one order of magnitude. The first and second metal films, respectively, have a multi-layered structure including a sub-layer made of Al or Al alloys.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: July 5, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kohsaku Yano, Tetsuya Ueda, Teruhito Ohnishi, Hiroshi Nishimura
  • Patent number: 5309021
    Abstract: A semiconductor device according to the present invention has reduced inductance on a power supply line, a grounding line, and signal lines. In this invention, to reduce the length of the power supply connection and that of the grounding connection, a power supply metal post and a grounding metal post are respectively provided on a power supply lead of a semiconductor chip and grounding lead of the semiconductor chip perpendicular to the leads. The metal posts protrude from the resin encapsulating the chip and are connected to lands or a conductive circuit pattern on a printed circuit board. Furthermore, a planar conductor commonly connecting the power supply or grounding potentials is provided.
    Type: Grant
    Filed: October 15, 1992
    Date of Patent: May 3, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Haruo Shimamoto, Jun Shibata, Toru Tachikawa, Tetsuya Ueda, Hiroshi Seki
  • Patent number: 5295752
    Abstract: A printer using double sheets of pressure sensitive paper includes a casing having an opening at its upper portion, a paper guide disposed in the opening of the casing, and a paper support disposed under the opening of the casing. The paper guide separates the printed double sheets of pressure sensitive paper into a receipt sheet and a journal sheet. The paper guide also operates to introduce the receipt sheet out of the casing through the opening and to guide the journal sheet in a predetermined direction within the casing with a front surface of the journal sheet exposed toward the opening. The paper support upwardly supports a rear surface of the journal sheet. Since the front surface of the journal sheet is exposed through the opening of the casing, a confirmation signature and/or correction signature can be handwritten on the front surface of the journal sheet.
    Type: Grant
    Filed: June 26, 1992
    Date of Patent: March 22, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinsuke Kawamoto, Osamu Miyajima, Tetsuya Ueda
  • Patent number: 5198884
    Abstract: A semiconductor device having a double-layer interconnection with contact portions between first and second metal films covered with at least a silicon nitride film is provided wherein an electromigration characteristic at the contact portions is improved. The improvement is achieved by defining a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at the contact portions is not larger than 2/5 of a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at non-contact portions. By this, the stress exerted on the second metal film is reduced to improve the electromigration life at the contact portions by about one order of magnitude. The first and second metal films are made of Al or Al-based alloys.
    Type: Grant
    Filed: March 27, 1991
    Date of Patent: March 30, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kohsaku Yano, Tetsuya Ueda, Teruhito Ohnishi, Hiroshi Nishimura
  • Patent number: 5196917
    Abstract: A carrier tape includes an insulating film supporting a plurality of leads. The film has a center device hole for receiving a semiconductor chip therein, a plurality of outer lead holes formed at the periphery of the center device hole, a lead supporting portion positioned between the center device hole and the outer lead holes, and a link portion positioned between a pair of adjacent outer lead holes and connected to the lead supporting portion for directing the flow of molten resin during encapsulation of the semiconductor chip. The link portion includes an opening or recess. The plurality of leads of the carrier tape are supported on the lead supporting of the film, with one end portion of each lead projecting into the center device hole of the film. During manufacture, a semiconductor chip having a plurality of electrodes is positioned within the center device hole, and the leads are electrically connected to respective electrodes of the semiconductor chip.
    Type: Grant
    Filed: December 4, 1989
    Date of Patent: March 23, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Kou Shimomura, Osamu Nakagawa, Seiji Takemura, Kazunari Michii
  • Patent number: 5180436
    Abstract: A microwave plasma film deposition system using the microwave plasma in a state in which a magnetic field is applied to a plasma cavity for generating the plasma. The microwave plasma film deposition system can stably deposit a metal thin film by separating an insulating window for supplying the microwave to the plasma cavity from a region to which the magnetic field is applied, limiting the form and the size of a waveguide and regulating the process conditions (mainly, the pressure of gases in the system).
    Type: Grant
    Filed: December 18, 1991
    Date of Patent: January 19, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuya Ueda, Naoki Suzuki, Kohsaku Yano
  • Patent number: 5166099
    Abstract: A manufacturing method for a semiconductor device in which an electrode of a semiconductor chip is electrically connected to an inner lead of a carrier tape. The electrodes of the semiconductor chip are brought into contact with the inner lead of the carrier tape. Bonding is performed with inner lead droop controlled to no more than 80 .mu.m.
    Type: Grant
    Filed: September 13, 1991
    Date of Patent: November 24, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Osami Nakagawa, Haruo Shimamoto, Yasuhiro Teraoka, Seiji Takemura
  • Patent number: 5157478
    Abstract: A packaged semiconductor device includes an insulating film having an opening, a semiconductor chip disposed in the opening of the insulating film and having a plurality of electrodes, a plurality of leads, each having one end connected to a corresponding electrode, the plurality of leads being supported on the insulating film, a heat radiator disposed opposite and spaced from the semiconductor chip, and a resin package body encapsulating the semiconductor chip and part of the heat radiator, leaving a surface of the heat radiator externally exposed and the second ends of the plurality of leads extending outwardly from the package.
    Type: Grant
    Filed: December 18, 1991
    Date of Patent: October 20, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Haruo Shimamoto, Yasuhiro Teraoka, Hideya Yagoura, Hiroshi Seki
  • Patent number: 5134093
    Abstract: A method of fabricating a semiconductor device is disclosed, which can prevent disconnection failures due to corrosion of aluminum-base alloy lines in the semiconductor device. First, an aluminum-base alloy film containing at least one kind of alloying element other than aluminum is formed on an insulating film which covers a semiconductor substrate. Before the surface of the aluminum-base alloy film is cleaned with fuming nitric acid, the surface treatment of the aluminum-base alloy film is performed using a plasma of an oxygen-base gas, to cover fully the surface of the aluminum-base alloy film with passivation film. Next, the given portions of the aluminum-base alloy film are selectively etched to form a line pattern. The surface treatment of the line pattern is performed using a plasma of an oxygen-base gas to cover fully the sides of the line pattern with passive film, before the surface of the line pattern is cleaned with fuming nitric acid.
    Type: Grant
    Filed: January 17, 1991
    Date of Patent: July 28, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Teruhito Onishi, Tetsuya Ueda