Patents by Inventor Tetsuzo Ueda

Tetsuzo Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7411232
    Abstract: A semiconductor photodetecting device is provided for enabling a solid-state image sensor to meet the requirements of higher quality imaging and more reduction in cost. The photodetecting device of the present invention includes: a semiconductor substrate; and an epitaxial layer formed on the semiconductor substrate by epitaxial growth. The epitaxial layer has a multilayer structure including: a first pn junction layer; a first insulating layer; a second pn junction layer; a second insulating layer; and a third pn junction layer. The first insulating layer and the second insulating layer have openings, and the first pn junction layer and the second pn junction layer are adjacent to each other through the openings of the first insulating layer which is placed in between these pn junction layers, and the second pn junction layer and the third pn junction layer are adjacent to each other through the openings of the second insulating layer which is placed in between these pn junction layers.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: August 12, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuzo Ueda, Seiichiro Tamai
  • Publication number: 20080179605
    Abstract: A nitride semiconductor light emitting device includes: a dielectric layered film over a substrate, the dielectric layered film being formed by stacking a plurality of dielectric films having different compositions; a semiconductor thin film formed of a single crystal over the dielectric layered film; and a pn junction diode structure over the semiconductor thin film, the pn junction diode structure being formed of a nitride semiconductor.
    Type: Application
    Filed: November 8, 2007
    Publication date: July 31, 2008
    Inventors: Yuji TAKASE, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda
  • Publication number: 20080179694
    Abstract: In FET, a second nitride semiconductor layer is provided on a first nitride semiconductor layer, and a source electrode and a drain electrode are each provided to have at least a portion thereof in contact with the second nitride semiconductor layer. A concave portion is formed in the upper surface of the second nitride semiconductor layer to be located between the source electrode and the drain electrode. A gate electrode is provided over the concave portion to cover the opening of the concave portion.
    Type: Application
    Filed: January 31, 2008
    Publication date: July 31, 2008
    Inventors: Kazushi NAKAZAWA, Satoshi NAKAZAWA, Tetsuzo UEDA, Tsuyoshi TANAKA, Masahiro HIKITA
  • Publication number: 20080179606
    Abstract: A nitride semiconductor light emitting device includes a substrate formed of silicon, an insulating film formed on the substrate and a single crystal thin film formed on the insulating film. On the single crystal film, a semiconductor laminated body including a light emitting layer of nitride semiconductor is formed.
    Type: Application
    Filed: January 9, 2008
    Publication date: July 31, 2008
    Inventors: Manabu USUDA, Tetsuzo Ueda, Kenji Orita
  • Publication number: 20080149940
    Abstract: A nitride semiconductor device includes: a substrate; a nitride semiconductor layer formed on a main surface of the substrate and having a channel region through which electrons drift in a direction parallel to the main surface; and a plurality of first electrodes and a plurality of second electrodes formed spaced apart from each other on an active region in the nitride semiconductor layer. An interlayer insulating film is formed on the nitride semiconductor layer. The interlayer insulating film has openings that respectively expose the first electrodes and has a planarized top surface. A first electrode pad is formed in a region over the active region in the interlayer insulating film and is electrically connected to the exposed first electrodes through the respective openings.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 26, 2008
    Inventors: Daisuke SHIBATA, Kazushi Nakazawa, Masahiro Hikita, Yasuhiro Uemoto, Tetsuzo Ueda, Manabu Yanagihara, Tsuyoshi Tanaka
  • Publication number: 20080149965
    Abstract: A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.
    Type: Application
    Filed: November 14, 2007
    Publication date: June 26, 2008
    Inventors: Kazuhiro KAIBARA, Masahiro HIKITA, Tetsuzo UEDA, Yasuhiro UEMOTO, Tsuyoshi TANAKA
  • Patent number: 7391798
    Abstract: A semiconductor laser device includes: an active layer formed on a substrate and including an AlGaAs layer; and an upper spacer layer formed at least one of above and below the active layer and including AlaGabIn1-a-bP (where 0?a?1, 0?b?1, and 0?a+b?1). The upper spacer layer has a composition enough to serve as a barrier layer against electrons injected into the active layer.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: June 24, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshikazu Onishi, Kazutoshi Onozawa, Tetsuzo Ueda
  • Publication number: 20080121896
    Abstract: The nitride semiconductor material according to the present invention includes a group III nitride semiconductor and a group IV nitride formed on the group III nitride semiconductor, where an interface between the group III nitride semiconductor and the group IV nitride has a regular atomic arrangement. Moreover, an arrangement of nitrogen atoms of the group IV nitride in the interface and an arrangement of group III atoms of the group III nitride semiconductor in the interface may be substantially identical.
    Type: Application
    Filed: April 23, 2007
    Publication date: May 29, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toshiyuki TAKIZAWA, Tetsuzo UEDA
  • Publication number: 20080121938
    Abstract: In a nitride semiconductor based bipolar transistor, a contact layer formed so as to contact an emitter layer is composed of n-type InAlGaN quaternary mixed crystals, the emitter layer and the contact layer are selectively removed so that the barrier height with the emitter formed thereon is small, and the ohmic electrode contact resistance can be lowered on the InAlGaN quaternary mixed crystals, for example, so that a WSi emitter electrode becomes an eave. A base electrode is formed by a self-aligned process using the emitter electrode as a mask. By such a configuration, the distance between the emitter and the edge of the base electrode is sufficiently shortened, and the base resistance can be lowered. As a result, a bipolar transistor having favorable high-frequency characteristics can be realized.
    Type: Application
    Filed: June 20, 2007
    Publication date: May 29, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tatsuo Morita, Tetsuzo Ueda
  • Publication number: 20080112448
    Abstract: A nitride semiconductor laser diode includes: a substrate made of silicon in which a plane orientation of a principal surface is a {100} plane; and a semiconductor that includes a plurality of semiconductor layers formed on the substrate and including an active layer, each of the plurality of semiconductor layers being made of group III nitride. The semiconductor has a plane parallel to a {011} plane which is a plane orientation of silicon as a cleaved facet, the cleaved facet forming a facet mirror.
    Type: Application
    Filed: November 9, 2007
    Publication date: May 15, 2008
    Inventors: Tetsuzo UEDA, Daisuke UEDA
  • Publication number: 20080087915
    Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.
    Type: Application
    Filed: July 24, 2007
    Publication date: April 17, 2008
    Inventors: Yasuhiro Uemoto, Masahiro Hikita, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda
  • Publication number: 20080079023
    Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.
    Type: Application
    Filed: August 7, 2007
    Publication date: April 3, 2008
    Inventors: Masahiro Hikita, Tetsuzo Ueda, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Publication number: 20080067546
    Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 20, 2008
    Inventors: Tomohiro MURATA, Hiroaki UENO, Hidetoshi ISHIDA, Tetsuzo UEDA, Yasuhiro UEMOTO, Tsuyoshi TANAKA, Daisuke UEDA
  • Publication number: 20080008220
    Abstract: It is an object of the present invention to provide a semiconductor laser device with high-yielding in which a clack generated in an epitaxial growth layer is restrained and to the manufacturing method thereof, the semiconductor laser device includes a GaN substrate 1, an n-type GaN layer 2, an n-type AlGaN cladding layer 3, a n-type GaN guide layer 4, an InGaN multiple quantum well active layer 5, an undoped-GaN guide layer 6, a p-type AlGaN electron overflow suppression layer 7, a p-type GaN guide layer 8, a SiO2 blocking layer 9, an Ni/ITO cladding layer electrode 10 as a transparent electrode, a Ti/Au pad electrode 11, and a Ti/Al/Ni/Au electrode 12. The SiO2 blocking layer 9 is formed above the InGaN multiple quantum well active layer 5 so as to have an opening. The Ni/ITO cladding layer electrode 10 is formed inside the opening, and which is transparent for the light from the InGaN multiple quantum well active layer, and serves as a cladding layer.
    Type: Application
    Filed: September 5, 2007
    Publication date: January 10, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tetsuzo UEDA, Masaaki YURI
  • Publication number: 20070278507
    Abstract: A field effect transistor includes a nitride semiconductor layered structure that is formed on a substrate and includes a capping layer made of a compound represented by a general formula of InxAlyGa1-yN (wherein 0<x?1, 0?y <1 and 0<x+y?1). A non-alloy source electrode and a non-alloy drain electrode are formed on the capping layer so as to be spaced from each other.
    Type: Application
    Filed: April 3, 2007
    Publication date: December 6, 2007
    Inventors: Satoshi Nakazawa, Tetsuzo Ueda
  • Publication number: 20070272945
    Abstract: A field-effect transistor has a so-called double heterostructure which is formed such that a channel layer through which electrons travel is provided between an electron supply layer and a liner layer, wherein a forbidden band width of the liner layer and a forbidden band width of the electron supply layer are broader than a forbidden bandwidth of the channel layer.
    Type: Application
    Filed: February 23, 2007
    Publication date: November 29, 2007
    Inventors: Hisayoshi Matsuo, Tetsuzo Ueda
  • Patent number: 7279751
    Abstract: It is an object of the present invention to provide a semiconductor laser device with high-yielding in which a clack generated in an epitaxial growth layer is restrained and to the manufacturing method thereof, the semiconductor laser device includes a GaN substrate 1, an n-type GaN layer 2, an n-type AlGaN cladding layer 3, a n-type GaN guide layer 4, an InGaN multiple quantum well active layer 5, an undoped-GaN guide layer 6, a p-type AlGaN electron overflow suppression layer 7, a p-type GaN guide layer 8, a SiO2 blocking layer 9, an Ni/ITO cladding layer electrode 10 as a transparent electrode, a Ti/Au pad electrode 11, and a Ti/Al/Ni/Au electrode 12. The SiO2 blocking layer 9 is formed above the InGaN multiple quantum well active layer 5 so as to have an opening. The Ni/ITO cladding layer electrode 10 is formed inside the opening, and which is transparent for the light from the InGaN multiple quantum well active layer, and serves as a cladding layer.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: October 9, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuzo Ueda, Masaaki Yuri
  • Publication number: 20070210332
    Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.
    Type: Application
    Filed: March 2, 2007
    Publication date: September 13, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroaki UENO, Tetsuzo Ueda, Yasuhiro Uemoto, Daisuke Ueda, Tsuyoshi Tanaka, Manabu Yanagihara, Yutaka Hirose, Masahiro Hikita
  • Patent number: 7268370
    Abstract: A phosphor that emits white light due to excitation by a light emitting diode capable of emitting blue or ultraviolet light includes: a substrate that allows transmission of visible light; and a semiconductor layer formed on the substrate.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: September 11, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tetsuzo Ueda
  • Publication number: 20070205407
    Abstract: A nitride semiconductor device includes a semiconductor stacked structure which is formed of a nitride semiconductor having a first principal surface and a second principal surface opposed to the first principal surface and which includes an active layer. The first principal surface of the semiconductor stacked structure is formed with a plurality of indentations whose plane orientations are the {0001} plane, and the plane orientation of the second principal surface is the {1-101} plane. The active layer is formed along the {1-101} plane.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 6, 2007
    Inventors: Hisayoshi Matsuo, Tatsuo Morita, Tetsuzo Ueda, Daisuke Ueda