Patents by Inventor Tetsuzo Ueda

Tetsuzo Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090121775
    Abstract: In a transistor, an AlN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type control layer 105, and a p-type contact layer 106 are formed in this order on a sapphire substrate 101. The transistor further includes a gate electrode 110 in ohmic contact with the p-type contact layer 106, and a source electrode 108 and a drain electrode 109 provided on the undoped AlGaN layer 104. By applying a positive voltage to the p-type control layer 105, holes are injected into a channel to increase a current flowing in the channel.
    Type: Application
    Filed: June 27, 2006
    Publication date: May 14, 2009
    Inventors: Daisuke Ueda, Tsuyoshi Tanaka, Yasuhiro Uemoto, Tetsuzo Ueda, Manabu Yanagihara, Masahiro Hikita, Hiroaki Ueno
  • Patent number: 7528423
    Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: May 5, 2009
    Assignee: Panasonic Corporation
    Inventors: Hiroaki Ueno, Tetsuzo Ueda, Yasuhiro Uemoto, Daisuke Ueda, Tsuyoshi Tanaka, Manabu Yanagihara, Yutaka Hirose, Masahiro Hikita
  • Publication number: 20090101920
    Abstract: A white light source has an excitation light source and a white light emitting element provided at a position which allows the transmission of light from the excitation light source to generate white light through irradiation with the light from the excitation light source. The white light emitting element has a sapphire substrate made of sapphire or the like which transmits visible light, an InGaAlN semiconductor layer formed on a surface of the sapphire substrate to emit red light through irradiation with visible light, and a fluorescent layer formed on the surface opposite to the surface provided with the semiconductor layer to emit yellow light or green light through irradiation with visible light.
    Type: Application
    Filed: December 22, 2008
    Publication date: April 23, 2009
    Inventor: Tetsuzo UEDA
  • Patent number: 7518153
    Abstract: A nitride semiconductor light emitting device includes a substrate formed of silicon, an insulating film formed on the substrate and a single crystal thin film formed on the insulating film. On the single crystal film, a semiconductor laminated body including a light emitting layer of nitride semiconductor is formed.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: April 14, 2009
    Assignee: Panasonic Corporation
    Inventors: Manabu Usuda, Tetsuzo Ueda, Kenji Orita
  • Publication number: 20090078943
    Abstract: A nitride semiconductor device mainly made of a nitride semiconductor material having excellent heat dissipation characteristics and great crystallinity and a method for manufacturing thereof are provided. The method for manufacturing the nitride semiconductor includes vapor-depositing a diamond layer on a silicon substrate, bonding an SOI substrate on a surface of the diamond layer, thinning the SOI substrate, epitaxially growing an GaN layer on the thinned SOI substrate, removing the silicon substrate, and bonding, on a rear-surface of the diamond layer, a material having a thermal conductivity greater than a thermal conductivity of the silicon substrate. The SOI substrate has an outermost surface layer and a silicon oxide layer. In the thinning, the SOI substrate is thinned by selectively removed through the silicon oxide layer, so that only the outermost surface layer is left.
    Type: Application
    Filed: September 18, 2008
    Publication date: March 26, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hidetoshi ISHIDA, Tetsuzo UEDA, Daisuke UEDA
  • Patent number: 7508001
    Abstract: The present invention aims to provide a long-lived semiconductor laser device with low threshold current and available for high-output operation in a blue-violet semiconductor laser device using a nitride semiconductor layer. In the semiconductor laser device, the following layers are sequentially formed on a GaN substrate 1: an n-type GaN layer 2; an n-type AlGaN cladding layer 3, a first n-type GaN guiding layer 4; and a p-type AlGaN blocking layer 6 (current-blocking layer), further a striped opening is formed on a portion of the p-type AlGaN blocking layer 6, a second n-type GaN guiding layer 5 is formed to cover the opening, and the following layers are sequentially formed on the second n-type GaN guiding layer 5: an InGaN multiple quantum well active layer 7; an undoped GaN guiding layer 8; a p-type AlGaN electron overflow suppression layer 9, a p-type AlGaN cladding layer 10, and a p-type GaN contact layer 11.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: March 24, 2009
    Assignee: Panasonic Corporation
    Inventors: Tetsuzo Ueda, Masaaki Yuri
  • Publication number: 20090045431
    Abstract: A light-emitting device includes an element structure including at least two semiconductor layers having mutually different conductivity types. A transparent p-side electrode of ITO is formed on the element structure. A bonding pad is formed on a region of the p-side electrode. An n-side electrode made of Ti/Au is formed on the surface of the element structure opposite to the p-side electrode. A metal film made of gold plating with a thickness of about 50 ?m is formed, using an Au layer in the n-side electrode as an underlying layer.
    Type: Application
    Filed: July 8, 2008
    Publication date: February 19, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tetsuzo UEDA, Masaaki Yuri
  • Publication number: 20090028563
    Abstract: An optical transmission/reception device includes at least one light emitting portion and at least one light receiving portion on the same substrate. The light emitting portion includes at least a lower multilayer reflector and an active layer provided on the lower multilayer reflector. A metal layer including a plurality of opening portions is provided in an upper portion of the light emitting portion. Each of the opening portions has a size smaller than a light emission wavelength of the light emitting portion.
    Type: Application
    Filed: July 25, 2008
    Publication date: January 29, 2009
    Inventors: Tatsuya TANIGAWA, Tetsuzo Ueda, Daisuke Ueda
  • Patent number: 7482641
    Abstract: A white light source has an excitation light source and a white light emitting element provided at a position which allows the transmission of light from the excitation light source to generate white light through irradiation with the light from the excitation light source. The white light emitting element has a sapphire substrate made of sapphire or the like which transmits visible light, an InGaAlN semiconductor layer formed on a surface of the sapphire substrate to emit red light through irradiation with visible light, and a fluorescent layer formed on the surface opposite to the surface provided with the semiconductor layer to emit yellow light or green light through irradiation with visible light.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: January 27, 2009
    Assignee: Panasonic Corporation
    Inventor: Tetsuzo Ueda
  • Patent number: 7465968
    Abstract: A semiconductor device includes: a first nitride semiconductor layer having at least one projection on an upper surface thereof; a second nitride semiconductor layer formed on a top surface of the projection of the first nitride semiconductor layer and having a higher carrier concentration than the first nitride semiconductor layer; a first electrode formed on the second nitride semiconductor layer so as to overhang like a canopy and functioning as one of a source and a drain; and a second electrode formed to the side of the projection on the first nitride semiconductor layer and functioning as a gate.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: December 16, 2008
    Assignee: Panasonic Corporation
    Inventors: Tetsuzo Ueda, Satoshi Nakazawa, Tatsuo Morita
  • Patent number: 7459377
    Abstract: The present invention aims at providing a method for dividing a substrate that is capable of dividing each substrate into chips in the same square-like form without causing chip breaking and capable of forming all cleaved facets flat. In the method for dividing a substrate of the present invention, an electron beam 1 with the intensity that causes a dislocation inside the substrate is irradiated to a substrate surface 2 to generate a crack starting from such dislocation, and a cleaved facet 5 is formed to divide the substrate.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: December 2, 2008
    Assignee: Panasonic Corporation
    Inventors: Tetsuzo Ueda, Daisuke Ueda
  • Patent number: 7459719
    Abstract: An optical semiconductor device includes an active layer having a quantum well structure including alternately stacked well layers and barrier layers with a larger band gap than the well layers. The band gap of each of the well layers and the barrier layers is constant, each well layer is uniformly provided with compression strain and each barrier layer is provided with large extension strain in a center portion thereof along the thickness direction and small extension strain in portions thereof in the vicinity of the well layers.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: December 2, 2008
    Assignee: Panasonic Corporation
    Inventors: Jun Shimizu, Tetsuzo Ueda, Toshikazu Onishi
  • Publication number: 20080277674
    Abstract: An LED bare chip which is one type of a semiconductor light emitting device (2) includes a multilayer epitaxial structure (6) composed of a p-GaN layer (12), an InGaN/GaN MQW light emitting layer (14) and an n-GaN layer (16). A p-electrode (18) is formed on the p-GaN layer (12), and an n-electrode (20) is formed on the n-GaN layer (16). An Au plating layer (4) is formed on the p-electrode (18). The Au plating layer (4) supports the multilayer epitaxial structure (6) and conducts heat generated in the light emitting layer (14). The Au plating layer (4) is electrically divided into two portions by a polyimide member (10). One of the two portions (4A) is connected to the p-electrode (18), to be constituted as an anode power supply terminal, and the other portion (4K) is connected to the n-electrode (20) by a wiring (22), to be constituted as a cathode power supply terminal.
    Type: Application
    Filed: November 1, 2004
    Publication date: November 13, 2008
    Inventors: Hideo Nagai, Tetsuzo Ueda, Masaaki Yuri
  • Publication number: 20080258243
    Abstract: A field effect transistor includes: a first nitride semiconductor layer having a plane perpendicular to a (0001) plane or a plane tilted with respect to the (0001) plane as a main surface; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider bandgap than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer; and a source electrode and a drain electrode formed so as to contact at least a part of the second nitride semiconductor layer or the third nitride semiconductor layer. A recess that exposes a part of the second nitride semiconductor layer is formed between the source electrode and the drain electrode in the third nitride semiconductor layer. A gate electrode is formed in the recess and an insulating film is formed between the third nitride semiconductor layer and the gate electrode.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 23, 2008
    Inventors: Masayuki Kuroda, Tetsuzo Ueda
  • Patent number: 7439595
    Abstract: A first SiO2 thin film, a tungsten gate electrode, and a second SiO2 thin film are selectively formed on a first n+-type GaN contact semiconductor layer in that order and in a multilayer film structure having the three layers, a stripe-shaped opening is formed. Via the opening, an undoped GaN channel semiconductor layer and the second n+-type GaN contact semiconductor layer are formed so that both the layers are regrown by, for example, metal organic chemical vapor deposition. A source electrode and a drain electrode are formed so as to contact the corresponding second and first n+-type GaN contact semiconductor layers. The regrown undoped GaN channel semiconductor layer and the regrown second n+-type GaN contact semiconductor layer are horizontally grown portions and hence, the contact area of the electrode can be made larger than the area of the opening.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: October 21, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tetsuzo Ueda
  • Patent number: 7435994
    Abstract: A spacer layer is formed on a single-crystal substrate and an epitaxially grown layer composed of a group III-V compound semiconductor layer containing a nitride or the like is further formed on the spacer layer. The epitaxially grown layer is adhered to a recipient substrate. The back surface of the single-crystal substrate is irradiated with a light beam such as a laser beam or a bright line spectrum from a mercury vapor lamp such that the epitaxially grown layer and the single-crystal substrate are separated from each other. Since the forbidden band of the spacer layer is smaller than that of the single-crystal substrate, it is possible to separate the thin semiconductor layer from the substrate by decomposing or fusing the spacer layer, while suppressing the occurrence of a crystal defect or a crack in the epitaxially grown layer.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: October 14, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tetsuzo Ueda
  • Patent number: 7435995
    Abstract: A phosphor that emits white light due to excitation by a light emitting diode capable of emitting blue or ultraviolet light includes: a substrate that allows transmission of visible light; and a semiconductor layer formed on the substrate.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: October 14, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tetsuzo Ueda
  • Publication number: 20080237605
    Abstract: A semiconductor device includes: a first semiconductor layer which is made of a first group III nitride semiconductor; a cap layer which is formed on the first semiconductor layer, which is made of a second group III nitride semiconductor, and which has an opening for exposing the first semiconductor layer; and a source electrode and a drain electrode which are formed on the cap layer so as to oppose to each other with the opening interposed. A gate electrode is formed on the bottom face of the opening with an insulating film interposed. The insulating film is formed on at least a part of the first semiconductor layer which is exposed through the opening.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 2, 2008
    Inventors: Tomohiro MURATA, Masayuki KURODA, Tetsuzo UEDA
  • Patent number: 7425732
    Abstract: A nitride semiconductor device includes an active layer including a first nitride semiconductor layer and a second nitride semiconductor layer which are periodically stacked, the second nitride semiconductor layer having a different composition from a composition of the first nitride semiconductor layer. An energy at a lower edge of a conduction band in the first nitride semiconductor layer is lower than an energy at a lower edge of a conduction band in the second nitride semiconductor layer, and an energy at an upper edge of a valence band in the first nitride semiconductor layer is lower than an energy at an upper edge of a valence band in the second nitride semiconductor layer.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: September 16, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuzo Ueda, Satoshi Nakazawa, Daisuke Ueda, Toshiyuki Takizawa
  • Publication number: 20080217625
    Abstract: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al0.25Ga0.75N layer, a sapphire substrate, and a buffer layer. A main surface of the n-type Al0.25Ga0.75N layer is on (0001) plane as a main surface, and concaves are arranged in a checkerboard pattern on the surface. The ohmic electrode contacts the sides of the concaves of the n-type Al0.25Ga0.75N layer, and the sides of the concaves are on non-polar surfaces such as (11-20) plane or (1-100) plane.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 11, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masayuki KURODA, Tetsuzo UEDA