Abstract: A voltage reference circuit (40) is provided for producing a low temperature-coefficient analogue trim value. A pair of EEPROMs (50 and 60) are arranged such that the trim value is the difference between two EEPROM transistor threshold voltages. The substantially temperature dependent components of threshold voltage cancel out leaving only the substantially temperature independent trim value. Therefor the temperature coefficient of the voltage reference circuit (40) is negligible.

Abstract: A voltage reference circuit (40) is provided for producing a low temerature-coefficient analogue trim value. A pair of EEPROMs (50 and 60) are arranged such that the trim value is the difference between two EEPROM transistor threshold voltages. The substantially temperature dependent components of threshold voltage cancel out leaving only the substantially temperature independent trim value. Therefor the temperature coefficient of the voltage reference circuit (40) is negligible.

Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).

Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).

Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).

Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).

Abstract: A semiconductor power device comprises a metal conductor (6) coupled to a semiconductor region (30) of the device, one or more bumps (8) formed in contact with the metal conductor (6) and a frame (14) formed of high conductivity material. The frame (14) comprises a connecting portion (18) for connecting to at least one of the one or more bumps (8) so as to provide an external connection to the semiconductor region (30) of the device.

Abstract: A control circuit for controlling a current switch to provide current to a load circuit, includes a hysteresis trigger circuit arranged to selectively switch on the current switch in dependence upon a control signal. A transistor is arranged to selectively provide an operating current to the hysteresis trigger circuit in dependence upon the control signal. In this way operating current is only supplied to the hysteresis trigger circuit when the control signal is high, such that the load circuit does not draw current when the control signal is low.

Abstract: A dynamic isolation circuit belonging to a monolithic integrated circuit comprising lateral transistors and vertical transistors. The lateral transistors are isolated by an isolating region connected to an isolating potential (V.sub.iso), these lateral transistors being connected up to voltages of a first polarity relative to a reference voltage (GND), the power terminal connected up to the rear face normally being at a potential (V.sub.out) of the first polarity relative to the reference voltage.