Abstract: A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).

Abstract: An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.

Abstract: A low pass filter having a first mode of operation and a second mode of operation. The low pass filter includes a charging circuit, a capacitor circuit, and low power circuitry coupled to the capacitor circuit and the charging circuit. The capacitor circuit stores a first differential voltage when the low pass filter is operating in the first mode of operation. The capacitor circuit stores a second differential voltage when the low pass filter is operating in the second mode of operation. The second differential voltage is substantially equal to the first differential voltage. The charging circuit may include a charging current source coupled to a current steering circuit. The low pass filter may further include a load circuit coupled to the current steering circuit and the low power circuitry. The low pass filter may be used in a delay locked loop circuit or a phase locked loop circuit.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal.

Abstract: A system for designing and optimizing integrated circuits. Design objectives and constraints are described as posynomial functions of the design parameters. The circuit design problem is then expressed as a special form of optimization problem called geometric programming, to which very efficient global optimization methods are applied. The present invention can thereby efficiently determine globally optimal circuit designs, or globally optimal trade-offs among competing performance measures such as, for example for an operational amplifier (op-amp), power, open-loop gain, and bandwidth. The present invention therefore yields automated synthesis of globally optimal circuit designs for a given circuit topology library, directly from specifications.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A temperature sensor is fabricated in an integrated circuit in combination with another device such as a microprocessor using a fabrication technology that is suitable for fabricating the device. Operation of the temperature sensor is based on the bandgap physics of semiconductors using a bandgap reference circuit and an amplifier that generate two measurement voltages, a voltage that is temperature-dependent and a voltage that is temperature-independent. The temperature sensor includes a bandgap power supply circuit that supplies a power supply voltage that is very stable to drive the temperature sensor so that the temperature sensor generates an output signal that is essentially independent of the power supply voltage.

Abstract: Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.

Abstract: Linear integrated circuit capacitors having greater capacitance per unit area by using lateral flux. One embodiment comprises a two metal layer capacitor wherein each metal layer is comprised of two capacitor conductive components. The capacitor conductive components are cross-coupled so that the total capacitance is the sum of the vertical flux between the metal layers, and the lateral flux along the edges between the two capacitor conductive components in each of the metal layers. The lateral flux between the capacitor conductive components in a single metal layer increases the capacitance per unit area and decreases the bottom-plate parasitic capacitance. Increasing the length of the common edge formed by capacitor conductive components in a metal layer increases the capacitance per unit area. In one lateral flux capacitor, each metal layer is comprised of a plurality of rows, alternate rows are coupled together such that lateral flux is generated between each of the rows.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: Linear integrated circuit capacitors having greater capacitance per unit area by using lateral flux. One embodiment comprises a two metal layer capacitor wherein each metal layer is comprised of two capacitor conductive components. The capacitor conductive components are cross-coupled so that the total capacitance is the sum of the vertical flux between the metal layers, and the lateral flux along the edges between the two capacitor conductive components in each of the metal layers. The lateral flux between the capacitor conductive components in a single metal layer increases the capacitance per unit area and decreases the bottom-plate parasitic capacitance. Increasing the length of the common edge formed by capacitor conductive components in a metal layer increases the capacitance per unit area. In one lateral flux capacitor, each metal layer is comprised of a plurality of rows, alternate rows are coupled together such that lateral flux is generated between each of the rows.

Abstract: A distributed electrostatic discharge (ESD) protection circuit for high frequency integrated circuits. A transmission line from an integrated circuit (IC) pad or package pin couples a plurality of ESD elements. The ESD elements, such as diodes, are distributed along the transmission line and coupled from the transmission line to ground or a power supply. The effective impedance of the transmission line and ESD elements is defined to match the impedance of an external line. Distributed ESD protection circuits provide a high frequency signal path that can be used well into the GHz frequency range and also provide effective ESD protection.

Abstract: A temperature sensor includes a bandgap reference circuit for providing a temperature-independent reference voltage, a biasing circuit that mirrors a current in the bandgap reference circuit for providing a temperature-dependent biasing voltage, and an amplifier responsive to the reference voltage and the biasing voltage for providing a temperature-dependent output voltage. Preferably, the temperature sensor is integral with a microprocessor and implemented in CMOS technology. The temperature sensor can be used, for instance, to reduce the clock speed of the microprocessor when the microprocessor temperature exceeds a predetermined temperature, or to store temperature-indicating data in non-volatile memory of the microprocessor to provide a thermal history of the microprocessor.

Abstract: Circuitry for adjusting the phase of an incoming periodic signal, typically a clock signal, throughout the entire period of the periodic signal. Phase adjustment circuitry has high resolution and employs only the number of delay elements in a delay chain necessary to span at least the period of the incoming signal or at least half the period in the case of dual chains receiving complementary clocks. Phase adjustment circuitry includes a delay chain of having a plurality of taps, a boundary detector for indicating when a tap is at a phase boundary of the incoming periodic signal, and selection circuitry for selecting one of the taps from the delay chain based on the boundary detector output and the selection circuitry input such that the selected tap is the desired phase adjustment of the incoming periodic signal and that the delay of the incoming signal is adjustable across its phase boundaries.

Abstract: A high gain, low voltage differential amplifier exhibiting extremely low common mode sensitivities includes a load element exhibiting a high differential resistance, but a low common mode resistance. The load element contains a positive differential load resistance and a negative differential load resistance, which offsets the positive differential load resistance. The output common mode level of the differential amplifier is one p-channel source to gate voltage drop below the power supply voltage prohibiting the common mode output voltage from drifting far from an active level. The differential amplifier also has application for use in a differential charge pump circuit. The high differential impedance of the differential amplifier allows the attainment of extremely small leakage, while a low common-mode impedance results in simplified biasing.

Abstract: A differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output complementary signals. The complementary signals output by the current switch have a voltage swing that centers about a predetermined voltage in response to the complementary input signals. The differential comparator further comprises first and second inverters coupled to receive the output complementary signals, wherein each inverter has a trip point voltage .[.equal.]. .Iadd.corresponding .Iaddend.to the predetermined voltage. The first and second inverters output full swing complementary output signals in response to the complementary signals output by the current switch.