Patents by Inventor Thomas H. Toifl
Thomas H. Toifl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9467313Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.Type: GrantFiled: June 22, 2015Date of Patent: October 11, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John F. Bulzacchelli, Pier Andrea Francese, Yong Liu, Thomas H. Toifl
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Patent number: 9461661Abstract: A linear reference analog to digital converter (ADC) network may include a first ADC operatively connected to a first sample and hold circuit. The linear reference ADC network may be configured to receive an input signal from the first sample and hold circuit and sample the input signal with a harmonic distortion. The linear reference ADC network may further include a reference ADC operatively connected to a second sample and hold circuit and configured to receive the input signal and sample the input signal with a second harmonic distortion. The linear reference ADC network may further include a combining module operatively connected to the first ADC and the reference ADC, the combining module configured to equalize a linearity of an output of the first ADC to a linearity of an output of the reference ADC, and output a combined output signal, and a circuit configured to output a calibrated output signal having calibrated harmonic distortion content.Type: GrantFiled: January 28, 2016Date of Patent: October 4, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas Kull, Danny Chen-Hsien Luu, Thomas H. Toifl
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Patent number: 9455695Abstract: A comparator for an analog-to-digital converter is provided. The comparator includes a differential amplifier unit that receives a sampling signal and provides an output signal, based on a voltage provided by the sampling signal. The differential amplifier unit includes an input stage that receives the sampling signal and integrates a current on the integration nodes based on potentials of the sampling signal. The comparator includes a sense amplifier coupled with the integration nodes that detects a potential difference and amplifies the potential difference to generate the output signal. The comparator includes a charge injection circuit (30) to inject equal charges into the integration nodes.Type: GrantFiled: August 25, 2015Date of Patent: September 27, 2016Assignee: International Business Machines CorporationInventors: Lukas Kull, Thomas H. Toifl
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Patent number: 9300498Abstract: A decision-feedback equalizer for use in a receiving unit of an incoming data stream and for providing a stream of bit data outputs includes a number of comparators configured to perform a comparison related to a number of threshold values and related to a digitalized data sample and to obtain a comparison result; at least one correction block configured to receive the comparison result of a respective one of the comparators and to generate a plurality of intermediate results; and a multiplexer configured to select from the set of intermediate results depending on the output data history to provide the stream of bit data outputs.Type: GrantFiled: June 22, 2015Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: Thomas H. Toifl, Hazar Yüksel
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Patent number: 9300312Abstract: An analog-digital converter with successive approximation includes a capacitor array for being loaded by applying a given input signal potential and for providing a sampling potential, wherein capacitors of the capacitor array are serially coupled with switches. A decision latch is included for evaluating the sampling potential in a number of consecutive decision steps. The analog-digital converter also includes a logic unit for selectively changing the sampling potential by selectively switching switches associated to the capacitors of the capacitor array for each decision step based on an evaluation result of a previous decision step, wherein the switches are respectively coupled with a calibration switch.Type: GrantFiled: June 24, 2015Date of Patent: March 29, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas Kull, Thomas H. Toifl
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Patent number: 9288086Abstract: A decision-feedback equalizer for use in a receiving unit of an incoming data stream and for providing a stream of bit data outputs includes a number of comparators configured to perform a comparison related to a number of threshold values and related to a digitalized data sample and to obtain a comparison result; at least one correction block configured to receive the comparison result of a respective one of the comparators and to generate a plurality of intermediate results; and a multiplexer configured to select from the set of intermediate results depending on the output data history to provide the stream of bit data outputs.Type: GrantFiled: April 1, 2015Date of Patent: March 15, 2016Assignee: International Business Machines CorporationInventors: Thomas H. Toifl, Hazar Yüksel
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Patent number: 9288085Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.Type: GrantFiled: March 26, 2015Date of Patent: March 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John F. Bulzacchelli, Pier Andrea Francese, Yong Liu, Thomas H. Toifl
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Publication number: 20160065229Abstract: A comparator for an analog-to-digital converter is provided. The comparator includes a differential amplifier unit that receives a sampling signal and provides an output signal, based on a voltage provided by the sampling signal. The differential amplifier unit includes an input stage that receives the sampling signal and integrates a current on the integration nodes based on potentials of the sampling signal. The comparator includes a sense amplifier coupled with the integration nodes that detects a potential difference and amplifies the potential difference to generate the output signal. The comparator includes a charge injection circuit (30) to inject equal charges into the integration nodes.Type: ApplicationFiled: August 25, 2015Publication date: March 3, 2016Inventors: Lukas Kull, Thomas H. Toifl
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Patent number: 9258109Abstract: The invention relates to a phase rotation method for a clock recovery, comprising the steps of: providing a timing estimation value that indicates for each input data symbol at least whether an input data sample has been sampled early or late by a sampling clock signal; generating a phase offset value indicating a phase rotation of the sampling clock signal based on the timing estimation value; modifying the timing function value based on a change of the phase offset value, resulting in the timing estimation value.Type: GrantFiled: December 5, 2014Date of Patent: February 9, 2016Assignee: International Business Machines CorporationInventors: Pier A. Francese, Lukas Kull, Thomas H. Toifl
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Patent number: 9252785Abstract: Clock recovery for a data receiving unit is disclosed. Clock recovery can include obtaining an early/late signal from an incoming data stream. The early/late signal indicates if a set of one or more data samples of the incoming data stream tends to be earlier or later than an edge of a phase-rotated clock signal provided depending on a phase offset value. Clock recovery can include updating a phase rotation counter value in response to the early/late signal. Clock recovery can include determining the phase offset value depending on a rounded phase rotation counter value. The phase offset value can be further determined by selecting one of a set of options including maintaining, increasing, or decreasing the rounded phase rotation counter value. The selecting is performed depending on the early/late signal and depending on the phase rotation counter value.Type: GrantFiled: November 19, 2014Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Peter Buchmann, Pier Andrea Francese, Thomas H. Toifl
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Patent number: 9191018Abstract: An analog-digital converter with successive approximation includes a capacitor array for being loaded by applying a given input signal potential and for providing a sampling potential, wherein capacitors of the capacitor array are serially coupled with switches. A decision latch is included for evaluating the sampling potential in a number of consecutive decision steps. The analog-digital converter also includes a logic unit for selectively changing the sampling potential by selectively switching switches associated to the capacitors of the capacitor array for each decision step based on an evaluation result of a previous decision step, wherein the switches are respectively coupled with a calibration switch.Type: GrantFiled: February 18, 2015Date of Patent: November 17, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas Kull, Thomas H. Toifl
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Publication number: 20150312061Abstract: A decision-feedback equalizer for use in a receiving unit of an incoming data stream and for providing a stream of bit data outputs includes a number of comparators configured to perform a comparison related to a number of threshold values and related to a digitalized data sample and to obtain a comparison result; at least one correction block configured to receive the comparison result of a respective one of the comparators and to generate a plurality of intermediate results; and a multiplexer configured to select from the set of intermediate results depending on the output data history to provide the stream of bit data outputs.Type: ApplicationFiled: April 1, 2015Publication date: October 29, 2015Inventors: Thomas H. Toifl, Hazar Yüksel
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Publication number: 20150312063Abstract: A decision-feedback equalizer for use in a receiving unit of an incoming data stream and for providing a stream of bit data outputs includes a number of comparators configured to perform a comparison related to a number of threshold values and related to a digitalized data sample and to obtain a comparison result; at least one correction block configured to receive the comparison result of a respective one of the comparators and to generate a plurality of intermediate results; and a multiplexer configured to select from the set of intermediate results depending on the output data history to provide the stream of bit data outputs.Type: ApplicationFiled: June 22, 2015Publication date: October 29, 2015Inventors: Thomas H. Toifl, Hazar Yüksel
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Publication number: 20150312064Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.Type: ApplicationFiled: June 22, 2015Publication date: October 29, 2015Inventors: John F. Bulzacchelli, Pier Andrea Francese, Yong Liu, Thomas H. Toifl
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Publication number: 20150295586Abstract: An analog-digital converter with successive approximation includes a capacitor array for being loaded by applying a given input signal potential and for providing a sampling potential, wherein capacitors of the capacitor array are serially coupled with switches. A decision latch is included for evaluating the sampling potential in a number of consecutive decision steps. The analog-digital converter also includes a logic unit for selectively changing the sampling potential by selectively switching switches associated to the capacitors of the capacitor array for each decision step based on an evaluation result of a previous decision step, wherein the switches are respectively coupled with a calibration switch.Type: ApplicationFiled: June 24, 2015Publication date: October 15, 2015Inventors: Lukas Kull, Thomas H. Toifl
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Publication number: 20150295736Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.Type: ApplicationFiled: March 26, 2015Publication date: October 15, 2015Inventors: John F. Bulzacchelli, Pier Andrea Francese, Yong Liu, Thomas H. Toifl
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Publication number: 20150244383Abstract: An analog-digital converter with successive approximation includes a capacitor array for being loaded by applying a given input signal potential and for providing a sampling potential, wherein capacitors of the capacitor array are serially coupled with switches. A decision latch is included for evaluating the sampling potential in a number of consecutive decision steps. The analog-digital converter also includes a logic unit for selectively changing the sampling potential by selectively switching switches associated to the capacitors of the capacitor array for each decision step based on an evaluation result of a previous decision step, wherein the switches are respectively coupled with a calibration switch.Type: ApplicationFiled: February 18, 2015Publication date: August 27, 2015Inventors: Lukas Kull, Thomas H. Toifl
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Publication number: 20150180648Abstract: The invention relates to a phase rotation method for a clock recovery, comprising the steps of: providing a timing estimation value that indicates for each input data symbol at least whether an input data sample has been sampled early or late by a sampling clock signal; generating a phase offset value indicating a phase rotation of the sampling clock signal based on the timing estimation value; modifying the timing function value based on a change of the phase offset value, resulting in the timing estimation value.Type: ApplicationFiled: December 5, 2014Publication date: June 25, 2015Inventors: Pier A. Francese, Lukas Kull, Thomas H. Toifl
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Publication number: 20150146830Abstract: Clock recovery for a data receiving unit is disclosed. Clock recovery can include obtaining an early/late signal from an incoming data stream, wherein the early/late signal indicates if a set of one or more data samples of the incoming data stream tends to be earlier or later than an edge of a phase-rotated clock signal provided depending on a phase offset value. Clock recovery can include updating a phase rotation counter value in response to the early/late signal. Clock recovery can include determining the phase offset value depending on a rounded phase rotation counter value. The phase offset value can be further determined by selecting one of a set of options including maintaining, increasing, or decreasing the rounded phase rotation counter value, wherein the selecting is performed depending on the early/late signal and depending on the phase rotation counter value.Type: ApplicationFiled: November 19, 2014Publication date: May 28, 2015Inventors: Peter Buchmann, Pier Andrea Francese, Thomas H. Toifl
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Patent number: 9041573Abstract: A sampling and interleaving stage device for use in an analog-digital-converter and for providing a sampling output signal and an analog-to-digital-converter. The sampling and interleaving stage device for use in an analog-digital-converter, including: a receiving unit having a clock unit with a plurality of clock-driven switches for receiving an input signal; for each of the plurality of clock-driven switches, a first demultiplexer, for receiving the input signal via a clock-driven switch and for providing a number of first demultiplexer outputs; for a first demultiplexer output, at least one storage element for a stored input potential depending on the input signal; and an output demultiplexer for receiving an indication about the stored input potential and for outputting a corresponding sampling output signal to a respective sampling output.Type: GrantFiled: March 18, 2014Date of Patent: May 26, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas Kull, Thomas H Toifl