Abstract: The communication system having a transmitter and a receiver, wherein the transmitter and the receiver are coupled by a clock channel and a data channel, wherein the clock channel is shorter than the data channel and wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by the delayed jitter signal.

Abstract: A system and method for cross talk compensation in serial link busses, the method including: evaluating if a positive potential or a negative potential is being received by a receiver of a victim from an aggressor is dominant; measuring the distance between an incident signal and a decision threshold to obtain a positive or negative value; and using the positive or negative sign as a recovered bit value if positive potential or a negative potential is being received by a receiver of a victim from an aggressor is not dominant and using the sign of the positive potential or a negative potential that is being received by a receiver of a victim from an aggressor if this is dominant.

Abstract: The forward error correction based clock and data recovery system includes a data latch for intermediately storing received data, which is triggered by a sampling clock. The system further includes an error determination unit for determining whether which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal. Furthermore, the system includes a clock generator for generating the sampling clock depending on the correction signal.

Abstract: A sampling clock signal controller for receivers of digital data is disclosed. Specific bit patterns of a data waveform can be identified, and stored time samples of the waveform that correspond to the specific bit patterns can be analyzed to improve the timing of a sampling clock signal. These “time-amplitude” samples on known bit patterns can be utilized to determine if a sample on the data waveform should be taken before the center of the eye pattern, at the center of the eye pattern, or after the center of the eye pattern and by what time change. Accordingly, a single low power clock can be utilized to adjust the timing of the sample clock such that improved communication scan be achieved. Such a single clock system has reduced power requirements and increased accuracy.

Abstract: A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the CDR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.

Abstract: A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.

Abstract: A system and method for cross talk compensation in serial link busses, the method comprising: evaluating if a positive potential or a negative potential is being received by a receiver of a victim from an aggressor is dominant; measuring the distance between an incident signal and a decision threshold to obtain a positive or negative value; and using the positive or negative sign as a recovered bit value if positive potential or a negative potential is being received by a receiver of a victim from an aggressor is not dominant and using the sign of the positive potential or a negative potential that is being received by a receiver of a victim from an aggressor if this is dominant.

Abstract: A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.

Abstract: A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.

Abstract: A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.

Abstract: To create a broad band spectrometer, a plurality of individual antenna based bolometers are fabricated on the surface of a single spectrometer chip, each bolometer having an individual antenna which is sized differently from all others, thus being responsive to a generally unique frequency of radiation. Each antenna is coupled to a related transistor, which is easily formed using CMOS technology. The antennas are connected to opposite sides of a transistor gate, thus creating a termination resistor for the particular antenna. Multiple outputs from the various antennas are then coupled, thus providing responsiveness to electromagnetic radiation of a very broad spectrum.

Abstract: A method and system for decision feedback equalization for digital transmission systems is provided. Low-power integrating decision feedback equalization with fast switched-capacitor paths are used, for suppressing intersymbol interference (ISI) due to past data symbols. The decision feedback equalization involves performing current-integrating decision feedback equalization at low-power employing a fast capacitively coupled feed-forward path at the output of a current-integrating buffer and inducing voltage changes by charge redistribution via coupled switching capacitors, and performing a voltage digital-to-analog conversation to determine a feedback coefficient as a coupling voltage. Then switches are reset to a pre-charge coupling voltage in the buffers to eliminate residual ISI caused by signal history, thereby achieving current integrating buffering with switched-capacitor feedback during the integration, and the capacitive switches are triggered by previous symbols.

Abstract: The forward error correction based clock and data recovery system according to the invention comprises a data latch (16) for intermediately storing received data, which is triggered by a sampling clock (sclk). The system further comprises an error determination unit (20, 21) for determining whether and which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal (ctrl). Furthermore, the system comprises a clock generator (23, 24, 25) for generating the sampling clock (sclk) depending on the correction signal (ctrl).

Abstract: A current-integrating amplifier is provided. The current-integrating amplifier comprises a pair of input voltage nodes having a voltage difference there between; A pair of current sources that generate a current that produces a voltage drop over a resistor that corresponds to an equivalent voltage difference between the pair of input voltage nodes; a pair of output voltage nodes; a pair of pMOSFETs connected to the pair of output voltage nodes; a first pair of nMOSFETs connected the pair of output voltage nodes, the pair of pMOSFETS, the pair of input voltage nodes, a resistor, and a second pair of nMOSFETS; a resistor connected to the pair of current sources; a second pair of nMOSFETs connected to the first and third pairs of nMOSFETs; and a third pair of nMOSFETs connected to the second pair of nMOSFETs and connected to a bias generator that provides a predetermined constant current.

Abstract: A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.

Abstract: According to one embodiment of the present invention an analog to digital converter comprises a track and hold unit, a plurality of current-integrating voltage shifters connected to the track and hold unit, a plurality of latches connected to the plurality of current-integrating voltage shifters, wherein a voltage offset of each latch in the plurality of latches is adjustable, wherein each current-integrating voltage shifter in the plurality of current-integrating voltage shifters drives a latch of the plurality of latches, wherein each current-integrating voltage shifter in the plurality of current-integrating voltage shifters corresponds to a voltage range, and wherein each latch connected to a current-integrating voltage shifter corresponds to a portion of the voltage range of the current-integrating voltage shifter.

Abstract: An integrated circuit for a memory input/output (I/O) pin has five different modes of operation. The memory chip is enabled to operate with unbuffered (or registered) dual inline memory modules (DIMMs) as well as fully buffered DIMMs. A T-coil circuit equalizes the capacitive loading of the high-speed functions. An exemplary embodiment provides a memory chip containing a multi-functional physical I/O circuit that can act as power or ground; as a DDR2 or DDR3 interface; as a high-speed differential receiver; or as a high-speed differential transmitter.

Abstract: To create a broad band spectrometer, a plurality of individual antenna based bolometers are fabricated on the surface of a single spectrometer chip, each bolometer having an individual antenna which is sized differently from all others, thus being responsive to a generally unique frequency of radiation. Each antenna is coupled to a related transistor, which is easily formed using CMOS technology. The antennas are connected to opposite sides of a transistor gate, thus creating a termination resistor for the particular antenna. Multiple outputs from the various antennas are then coupled, thus providing responsiveness to electromagnetic radiation of a very broad spectrum.

Abstract: A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.

Abstract: A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.