Patents by Inventor Thomas H. Toifl
Thomas H. Toifl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8917762Abstract: A decision feedback equalizer (DFE) slice for a receiver includes a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages, each of the first and second multiplexer stages including 4 comparator latches, each of the 4 comparator latches having a programmable offset; and a multiplexer that receives 4 comparator latch outputs from the 4 comparator latches and outputs a multiplexer stage output, wherein the multiplexer is controlled by previous symbol decisions dn-2 and dn-3; and wherein the 3 speculative taps further comprise a 2:1 decision multiplexer stage that receives the multiplexer stage outputs of the first and second multiplexer stages and is controlled by a previous symbol decision dn-1 to output a slice output signal dn.Type: GrantFiled: June 1, 2012Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Pier A. Francese, Christian I. Menolfi, Thomas H. Toifl
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Patent number: 8867668Abstract: A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier.Type: GrantFiled: November 8, 2013Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Troy J. Beukema, Gautam Gangasani, Thomas H. Toifl
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Publication number: 20140292551Abstract: A sampling and interleaving stage device for use in an analog-digital-converter and for providing a sampling output signal and an analog-to-digital-converter. The sampling and interleaving stage device for use in an analog-digital-converter, including: a receiving unit having a clock unit with a plurality of clock-driven switches for receiving an input signal; for each of the plurality of clock-driven switches, a first demultiplexer, for receiving the input signal via a clock-driven switch and for providing a number of first demultiplexer outputs; for a first demultiplexer output, at least one storage element for a stored input potential depending on the input signal; and an output demultiplexer for receiving an indication about the stored input potential and for outputting a corresponding sampling output signal to a respective sampling output.Type: ApplicationFiled: March 18, 2014Publication date: October 2, 2014Applicant: International Business Machines CorporationInventors: Lukas Kull, Thomas H. Toifl
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Patent number: 8749268Abstract: An inverter-type high speed driver circuit having a first inverter branch and a second inverter branch wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor. The impedance tuning units are configured to adapt the conductivity of the respective inverter branch to set the output impedance of the driver circuit and each of the impedance tuning units is controlled in accordance with a data stream.Type: GrantFiled: November 29, 2012Date of Patent: June 10, 2014Assignee: International Business Machines CorporationInventors: Christian I. Menolfi, Thomas H. Toifl
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Publication number: 20140133604Abstract: A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier.Type: ApplicationFiled: November 8, 2013Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Troy J. Beukema, Gautam Gangasani, Thomas H. Toifl
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Patent number: 8674737Abstract: A slew rate control circuit configured to control a slew rate of driver circuit comprises a clock delay module that receives a half-rate clock signal and that includes a plurality of delay cells configured to generate a plurality of respective delayed clock signals each having a different time delay from one another. A driver module includes a plurality of multiplexers in electrical communication with a respective data cell to receive a corresponding delayed clock signal. The multiplexers are configured to output a respective full-rate data stream in response to the delayed clock signal. The slew driver module further includes an output stage circuit in electrical communication with each multiplexer to combine each full-rate data stream and to generate a final step-wise driving signal that controls the slew rate.Type: GrantFiled: September 7, 2012Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Marcel A. Kossel, Michael A. Sorna, Thomas H. Toifl, Glen A. Wiedemeier
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Publication number: 20140070864Abstract: A slew rate control circuit configured to control a slew rate of driver circuit comprises a clock delay module that receives a half-rate clock signal and that includes a plurality of delay cells configured to generate a plurality of respective delayed clock signals each having a different time delay from one another. A driver module includes a plurality of multiplexers in electrical communication with a respective data cell to receive a corresponding delayed clock signal. The multiplexers are configured to output a respective full-rate data stream in response to the delayed clock signal. The slew driver module further includes an output stage circuit in electrical communication with each multiplexer to combine each full-rate data stream and to generate a final step-wise driving signal that controls the slew rate.Type: ApplicationFiled: September 7, 2012Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marcel A. Kossel, Michael A. Sorna, Thomas H. Toifl, Glen A. Wiedemeier
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Patent number: 8633764Abstract: An apparatus comprises an amplifier circuit comprising at least one output node and a common-mode restoration circuit capacitively coupled to the at least one output node of the amplifier circuit. The common-mode restoration circuit is configured to introduce at least one common-mode restoring signal onto the output node, wherein the at least one common-mode restoring signal transitions in correspondence with an operation interval of the amplifier circuit and thereby compensates for a common-mode voltage drop on the at least one output node of the amplifier circuit. In one example, the amplifier circuit may comprise a current-integrating amplifier circuit, and the operation interval may comprise an integration interval.Type: GrantFiled: June 10, 2011Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Ankur Agrawal, John F. Bulzacchelli, Thomas H. Toifl
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Publication number: 20130322512Abstract: A decision feedback equalizer (DFE) slice for a receiver includes a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages, each of the first and second multiplexer stages including 4 comparator latches, each of the 4 comparator latches having a programmable offset; and a multiplexer that receives 4 comparator latch outputs from the 4 comparator latches and outputs a multiplexer stage output, wherein the multiplexer is controlled by previous symbol decisions dn-2 and dn-3; and wherein the 3 speculative taps further comprise a 2:1 decision multiplexer stage that receives the multiplexer stage outputs of the first and second multiplexer stages and is controlled by a previous symbol decision dn-1 to output a slice output signal dn.Type: ApplicationFiled: June 1, 2012Publication date: December 5, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier A. Francese, Christian I. Menolfi, Thomas H. Toifl
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Patent number: 8599966Abstract: A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier.Type: GrantFiled: June 30, 2011Date of Patent: December 3, 2013Assignee: International Business Machines CorporationInventors: Troy J. Beukema, Gautam Gangasani, Thomas H. Toifl
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Patent number: 8576106Abstract: An analog-digital converter includes converter units and a control unit. The converter units each including a comparator for performing a comparison using an input voltage, one or more capacitor ladders each having a signal line connected with first terminals of capacitors and with one input of the comparator, and switches each of which is associated with one of the capacitors, connected to a second terminal of the respective capacitor with a first or a second reference potential, the input voltage being shifted when switching one or more of the switches. The control unit controls the number of converter units, and to set the switching states of the plurality of switches in conversion cycles and to obtain comparison results from each of the comparators in a comparison subsequent to each setting of the switching states.Type: GrantFiled: November 29, 2011Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Martin Leo Schmatz, Thomas H. Toifl
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Patent number: 8536917Abstract: A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.Type: GrantFiled: February 7, 2012Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Juergen Hertle, Christian I. Menolfi, Thomas H. Toifl
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Patent number: 8520724Abstract: A method for sending data to a memory chip includes receiving data at a data transmitter disposed on a memory hub chip, applying Tomlinson-Harashima precoding (THP) equalization to the data prior to transmitting the data; and transmitting the data from the transmitter to a memory chip.Type: GrantFiled: August 31, 2012Date of Patent: August 27, 2013Assignee: International Business Machines CorporationInventors: Marcel A. Kossel, Thomas H. Toifl
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Publication number: 20130200934Abstract: A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.Type: ApplicationFiled: February 7, 2012Publication date: August 8, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Juergen Hertle, Christian I. Menolfi, Thomas H. Toifl
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Patent number: 8428110Abstract: A system includes a memory hub chip including a Tomlinson-Harashima precoding (THP) equalizer portion operative to perform transmitter equalization at the memory hub chip and send data from to a memory chip.Type: GrantFiled: March 25, 2011Date of Patent: April 23, 2013Assignee: International Business Machines CorporationInventors: Marcel A. Kossel, Thomas H. Toifl
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Publication number: 20130002347Abstract: A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Troy J. Beukema, Gautam Gangasani, Thomas H. Toifl
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Publication number: 20120327995Abstract: A method for sending data to a memory chip includes receiving data at a data transmitter disposed on a memory hub chip, applying Tomlinson-Harashima precoding (THP) equalization to the data prior to transmitting the data; and transmitting the data from the transmitter to a memory chip.Type: ApplicationFiled: August 31, 2012Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marcel A. Kossel, Thomas H. Toifl
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Publication number: 20120313703Abstract: An apparatus comprises an amplifier circuit comprising at least one output node and a common-mode restoration circuit capacitively coupled to the at least one output node of the amplifier circuit. The common-mode restoration circuit is configured to introduce at least one common-mode restoring signal onto the output node, wherein the at least one common-mode restoring signal transitions in correspondence with an operation interval of the amplifier circuit and thereby compensates for a common-mode voltage drop on the at least one output node of the amplifier circuit. In one example, the amplifier circuit may comprise a current-integrating amplifier circuit, and the operation interval may comprise an integration interval.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: International Business Machines CorporationInventors: Ankur Agrawal, John F. Bulzacchelli, Thomas H. Toifl
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Publication number: 20120243599Abstract: A system includes a memory hub chip including a Tomlinson-Harashima precoding (THP) equalizer portion operative to perform transmitter equalization at the memory hub chip and send data from to a memory chip.Type: ApplicationFiled: March 25, 2011Publication date: September 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marcel A. Kossel, Thomas H. Toifl
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Publication number: 20120133541Abstract: An analog-digital converter includes converter units and a control unit. The converter units each including a comparator for performing a comparison using an input voltage, one or more capacitor ladders each having a signal line connected with first terminals of capacitors and with one input of the comparator, and switches each of which is associated with one of the capacitors, connected to a second terminal of the respective capacitor with a first or a second reference potential, the input voltage being shifted when switching one or more of the switches. The control unit controls the number of converter units, and to set the switching states of the plurality of switches in conversion cycles and to obtain comparison results from each of the comparators in a comparison subsequent to each setting of the switching states.Type: ApplicationFiled: November 29, 2011Publication date: May 31, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Leo Schmatz, Thomas H. Toifl