Abstract: The forward error correction based clock and data recovery system includes a data latch for intermediately storing received data, which is triggered by a sampling clock. The system further includes an error determination unit for determining whether which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal. Furthermore, the system includes a clock generator for generating the sampling clock depending on the correction signal.

Abstract: A sampling clock signal controller for receivers of digital data is disclosed. Specific bit patterns of a data waveform can be identified, and stored time samples of the waveform that correspond to the specific bit patterns can be analyzed to improve the timing of a sampling clock signal. These “time-amplitude” samples on known bit patterns can be utilized to determine if a sample on the data waveform should be taken before the center of the eye pattern, at the center of the eye pattern, or after the center of the eye pattern and by what time change. Accordingly, a single low power clock can be utilized to adjust the timing of the sample clock such that improved communication scan be achieved. Such a single clock system has reduced power requirements and increased accuracy.

Abstract: A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the DRR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.

Abstract: A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.

Abstract: Systems for making impedance adjustments that will auto-tune a communication path is disclosed. The method can utilize time domain reflectometry (TDR) to acquire data about impedance mismatches and can adjust the termination impedances based on the acquired data. A system is also disclosed that has an isolator to decouple a first adjustable resistor from a transmission path in a first mode and couple the first adjustable resistor to the path in a second mode. The system can have a test transmitter to create a first current on the path in the first mode and to create a second current having twice the current in a second mode, wherein a detector can detect a first voltage during the first mode and a second voltage in the second mode as the first adjustable resistive load is adjusted in the second mode until it reaches a value matching the first voltage detected in the first mode.

Abstract: A multi-Gigahertz, low jitter phase locked loop (PLL) with adjustable gain is disclosed. In one embodiment, properties of a fVCO signal of a PLL can be acquired. Properties can include the occurrences of different types of jitter on the fVCO signal and the lock status of the PLL. A gain control module can control at least a portion of the PLL based on an analysis of the acquired properties. For example, when the loop is locked or when there is loop filter leakage, the gain of a charge pump in the PLL can be reduced. When a charge pump mismatch is detected based on the acquired properties, additional control signals can be provided to the charge pump to correct the mismatch.

Abstract: A high speed, low jitter phase locked loop (PLL) with feed forward phase frequency detection is disclosed. The phase frequency detector can include a phase difference sensor providing an output signal indicating a phase difference duration between a rising edge of a reference signal and a rising edge of a feedback signal. The apparatus can also include a lead lag sensor to provide an out put signal indicating when the reference signal leads the feedback signal. In addition, a steering logic module can be coupled to the output of the phase difference sensor and the lead lag sensor and the steering logic module can steer the phase difference duration signal to a first output when the reference signal leads the feedback signal, and can steer the phase difference signal to a second output when the reference signal lags the feedback signal.

Abstract: The present invention provides integrated line drivers useable for driving data signals with high data rates wherein the area consumption of the line driver is minimized and wherein the influence of electrostatic discharge devices and process tolerances are minimized too. An example of an integrated line driver according to the invention comprises a first driver stage followed by a second driver stage, and a feedback unit forming with the second driver stage a control loop. The integrated line drivers are useable for driving data signals with high data rates wherein the area consumption of the line driver is minimized and wherein the influence of ESD devices and process tolerances are minimized. Advantageously, the integrated line driver according to the invention complies with chip design methodologies, where 10 or more routing metal layers are used.

Abstract: A self aligning trailer hitch, used by a driver alone without creating any personal lifting force, to couple and decouple a towing vehicle and a trailer, has a multiple piece assembly of a socket for securement to a towing vehicle, having a rotatable claw, which has a spherical recessed surface adapted to receive a portion of a lower ball of a vertical dual ball assembly, which is secured to a towed vehicle. Upon hitching the vehicles together, the rotatable claw contacts the lower ball, when this socket is moving horizontally, during movement of a towing vehicle toward the towed vehicle, causing the lower ball to be repositioned upwardly and over center, while being guided in a vertical plane, and then held in the radially upwardly repositioned spherical recessed surface of the rotatable claw. A three dimensional ramp guides the lower ball to fully contact the spherical recessed surface of the rotatable claw.