Abstract: According to an embodiment, a programmable logic circuit is described comprising a first data bit input to receive a first data bit a and a second data bit input to receive a second data bit b, a first program bit input to receive a first program bit p1, a second program bit input to receive a second program bit p2, a third program bit input to receive a third program bit p3 and a fourth program bit to receive a fourth program bit p4 and an output configured to output ( ( ( a ? b ) ? ( p 1 ? a ) ? ( p 2 ? b ) ) _ ? ( p 3 ? b ? a ) ) ? ( a ? b ? p 4 ) _ .

Abstract: According to an embodiment, a circuit is described comprising a plurality of flip-flops, a control circuit configured to provide a control signal to each flip-flop of the plurality of flip-flops and an integrity checking circuit connected to the control circuit and to the plurality of flip-flops configured to check whether the flip-flops receive the control signal as provided by the control circuit.

Abstract: According to one embodiment, a semiconductor chip is described including a semiconductor chip body and a semiconductor chip circuit on the body and including a first circuit path coupled to a first and a second node and including at least two gate-insulator-semiconductor structures and a second circuit path coupled to the first and the second node and including at least two gate-insulator-semiconductor structures. The first and the second circuit path are connected to set the first and the second node to complementary logic states. In each of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured as field effect transistor. In at least one of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured to connect the circuit path to the semiconductor body.

Abstract: A zero detection circuit includes a chain of masked OR circuits. Each masked OR circuit includes data inputs. Each data input is configured to receive a respective data input bit. Each masked OR circuit further includes an input mask input to receive one or more input masking bits, an output mask input to receive an output masking bit and a data output. The zero detection circuit is configured to output a bit equal to an OR combination, masked with the output masking bit, of the data input bits, each demasked with an input masking bit of the one or more input masking bits. One of the inputs of each masked OR circuit except the first masked OR circuit of the chain of masked OR circuits is coupled to the data output of the masked OR circuit preceding the masked OR circuit in the chain of masked OR circuits.

Abstract: According to one embodiment, a chip has a circuit with at least one p channel field effect transistor (FET); at least one n channel FET; a first and a second power supply terminal; wherein the n channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the p channel FET; and the p channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the n channel FET; wherein the logic state of the gate of the p channel FET and of the n channel FET can only be changed by at least one of the first and second supply voltage to the circuit; and a connection coupled to the gate of the p channel FET or the n channel FET and a further component of the semiconductor chip.

Abstract: A delay circuit includes an electronic transmission element with a first input and a first output. The first input is coupled to the first output by two first switches wired in parallel. The first switches each have a control input, a second input and a second output. The second input is coupled to the second output by two second switches wired in parallel. The circuit further includes an input circuit to receive an input signal and feed the input signal to one of the transmission element inputs and feed the inverted input signal to the other of the transmission element inputs, and an output circuit. The output circuit is configured such that the output signal only changes in the case of a change in the input signal if the change in the input signal has brought about a change both at the first output and at the second output.

Abstract: In accordance with one embodiment, a method for accessing a memory is provided, including carrying out a first access to the memory and charging, for a memory cell, a bit line coupled to the memory cell to a value which is stored or to be stored in the memory cell, holding the state of the bit line until a second access, which follows the first access, and outputting the held state if the second access is a read access to the memory cell.

Abstract: According to one embodiment, a processing circuit is described including a first input path and a second input path, a processing element configured to receive a first input bit and a second input bit via the first input path and the second input path and configured to perform a logic operation which is commutative with respect to the first input bit and the second input bit and a sorter configured to distribute the first input bit and the second input bit to the first input path and the second input path according to a predetermined sorting rule.

Abstract: A chip having a substrate region having a substrate contact, an RS latch having two complementary nodes representing a storage state of the RS latch, a control circuit having a control input and configured to connect one of the complementary nodes to a supply potential depending on a potential at the control input, wherein the control input is connected to the substrate contact, and an output circuit connected to an output of the RS latch and configured to trigger an alarm depending on the storage state of the RS latch.

Abstract: According to one embodiment, a method for manufacturing a digital circuit is described comprising forming a modified RS master latch with an output for outputting an output signal comprising forming two field effect transistors which are virtually identical wherein the two formed field effect transistors are connected to each other in an RS latch type configuration and the respective threshold voltages of the two field effect transistors are set to be different from each other so that the output signal of the modified RS master latch in response to an RS latch forbidden input transition has a predetermined defined logic state, forming an RS slave latch having a set input and a reset input and connecting the set input or the reset input of the RS-slave latch to the output of the modified RS master latch.

Abstract: According to one embodiment, a physical uncloneable function circuit for providing a protected output bit is described including at least one physical uncloneable function circuit element configured to output a bit of a physical uncloneable function value, a physical uncloneable function bit output terminal and a coupling circuit connected between the physical uncloneable function circuit element and the physical uncloneable function bit output terminal configured to receive a control signal, supply the bit to the physical uncloneable function bit output terminal for a first state of the control signal and supply the complement of the bit to the physical uncloneable function bit output terminal for a second state of the control signal.

Abstract: According to one embodiment, a semiconductor chip is described including a semiconductor chip body and a semiconductor chip circuit on the body and including a first circuit path coupled to a first and a second node and including at least two gate-insulator-semiconductor structures and a second circuit path coupled to the first and the second node and including at least two gate-insulator-semiconductor structures. The first and the second circuit path are connected to set the first and the second node to complementary logic states. In each of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured as field effect transistor. In at least one of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured to connect the circuit path to the semiconductor body.

Abstract: According to an embodiment, a programmable logic circuit is described comprising a first data bit input to receive a first data bit a and a second data bit input to receive a second data bit b, a first program bit input to receive a first program bit p1, a second program bit input to receive a second program bit p2, a third program bit input to receive a third program bit p3 and a fourth program bit to receive a fourth program bit p4 and an output configured to output ( ( ( a ? b ) ? ( p 1 ? a ) ? ( p 2 ? b ) ) _ ? ( p 3 ? b ? a ) ) ? ( a ? b ? p 4 ) _ .

Abstract: According to an embodiment, a circuit is described comprising a plurality of flip-flops, a control circuit configured to provide a control signal to each flip-flop of the plurality of flip-flops and an integrity checking circuit connected to the control circuit and to the plurality of flip-flops configured to check whether the flip-flops receive the control signal as provided by the control circuit.

Abstract: A cryptographic processor is described comprising a processing circuit configured to perform a round function of an iterated cryptographic algorithm, a controller configured to control the processing circuit to apply a plurality of iterations of the round function on a message to process the message in accordance with the iterated cryptographic algorithm and a transformation circuit configured to transform the input of a second iteration of the round function following a first iteration of the round function of the plurality of iterations and to supply the transformed input as input to the second iteration wherein the transformation circuit is implemented using a circuit camouflage technique.

Abstract: According to one embodiment, a chip is described comprising a transistor level, a semiconductor region in, below, or in and below the transistor level, a test signal circuit configured to supply a test signal to the semiconductor region, a determiner configured to determine a behavior of the semiconductor region in response to the test signal and a detector configured to detect a change of geometry of the semiconductor region based on the behavior and a reference behavior of the semiconductor region in response to the test signal.

Abstract: According to an embodiment, an electronic transmission element is provided that has a first input and a first output. The first input is coupled to the first output by means of two first, parallel-connected complementary switches. The first switches each have a control input. The electronic transmission element further has a second input and a second output. The second input is coupled to the second output by means of two second, parallel-connected complementary switches. The second switches each have a control input. The first output is coupled to the control inputs of the second switches and the second output is coupled to the control inputs of the first switches.

Abstract: A method for reconstructing a first vector from a second vector includes: storing code for the row vectors according to a first code and a second code; correcting the row vectors of the second vector corresponding to the first vector so that the row vectors of the second vector have the same code as the row vectors of the first vector; calculating the code of the column vectors of the second vector according to the second code; comparing the code of the row vectors of the second vector with the code of the column vectors of the first vector; identifying the columns in which the first vector is unequal to the second vector; the rows in which the first vector is unequal to the second vector; and the components in which the first vector is not equal to the second vector, and correcting the components of the second vector.

Abstract: According to one embodiment, a chip is described comprising a substrate; an energy source configured to provide energy to the substrate; an energy receiver configured to receive energy from the energy source via the substrate and a determiner configured to determine a value of a parameter of the energy transmission between the energy source and the energy receiver, to check whether the value matches a predetermined value of the parameter and to output a signal depending on the result of the check.

Abstract: According to one embodiment, a method for manufacturing a digital circuit is described comprising forming a modified RS master latch with an output for outputting an output signal comprising forming two field effect transistors which are virtually identical wherein the two formed field effect transistors are connected to each other in an RS latch type configuration and the respective threshold voltages of the two field effect transistors are set to be different from each other so that the output signal of the modified RS master latch in response to an RS latch forbidden input transition has a predetermined defined logic state, forming an RS slave latch having a set input and a reset input and connecting the set input or the reset input of the RS-slave latch to the output of the modified RS master latch.