Abstract: A device includes a flip flop and a control circuit. The flip flop includes a flip flop data input terminal and a flip flop clock input terminal. The control circuit includes a control circuit data input terminal and a control circuit clock input terminal. The control circuit is configured to route, in a Data Processing Mode of the device, an incoming data signal from the control circuit data input terminal to the flip flop data input terminal and an incoming clock signal from the control circuit clock input terminal to the flip flop clock input terminal and to apply, in a Data Retention Mode of the device, a first given fixed signal value to the flip flop data input terminal independent of a value of the incoming data signal and a second given fixed signal value to the flip flop clock input terminal independent of a value of the incoming clock signal.

Abstract: Some embodiments show a storage circuit with fault detection. The storage circuit comprises, first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state.

Abstract: A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.

Abstract: An integrated circuit comprises a circuit used for storing or processing data and a radiation-sensitive thyristor structure configured to conditionally short two power supply terminals of the integrated circuit. The thyristor structure is configured to turn on in response to a region of the thyristor structure being irradiated with radiation to which the thyristor structure is sensitive, in order to establish an electrically conductive connection between a first power supply terminal of the power supply terminals of the integrated circuit and a second power supply terminal of the power supply terminals of the integrated circuit. The thyristor structure is further configured so that a power density of the radiation needed for turning on the thyristor structure is lower than a power density of the radiation needed for a change of data of the circuit used for storing or processing data.

Abstract: An integrated circuit comprises a circuit used for storing or processing data and a radiation-sensitive thyristor structure configured to conditionally short two power supply terminals of the integrated circuit. The thyristor structure is configured to turn on in response to a region of the thyristor structure being irradiated with radiation to which the thyristor structure is sensitive, in order to establish an electrically conductive connection between a first power supply terminal of the power supply terminals of the integrated circuit and a second power supply terminal of the power supply terminals of the integrated circuit. The thyristor structure is further configured so that a power density of the radiation needed for turning on the thyristor structure is lower than a power density of the radiation needed for a change of data of the circuit used for storing or processing data.

Abstract: Digital fault detection circuit with an input circuit having input and output, wherein a first signal state at the input causes a predetermined signal state at the output and a second signal state at the input leaves the output floating; a signal line with signal line input and output, wherein the signal line input is coupled to the output of the input circuit; a keeper circuit coupled to the signal line output and configured to keep the signal line at the predetermined signal state, after the signal state at the input has changed from the first signal state to the second signal state; and a fault detector cell, which is coupled to the signal line between the signal line input and the signal line output and which is configured to change the state of the signal line which is otherwise kept by the keeper circuit, in response to a fault.

Abstract: A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.

Abstract: A circuit arrangement having complementary data lines of a dual rail data bus, wherein in a regular operating phase the complementary data lines carry complementary signals, and in a precharge phase the complementary data lines assume an identical logic state or the same electrical potential. The circuit arrangement also has a device for detecting manipulation attempts, the device having a detector circuit, which outputs an alarm signal upon the occurrence of an identical logic state on both data lines in the regular operating phase.

Abstract: A memory cell for storing a binary state, the memory cell being adapted for storing a binary state based on a write indication and a binary write masking value and for storing a complementary binary state based on the write indication and a complementary binary write masking value.

Abstract: An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.

Abstract: Device for storing a binary state defined by a first binary value and a second binary value complementary thereto, the device capable of being queried by a query signal so as to output, in dependence on a binary masking state, the first binary value at a first output and the second binary value at a second output or vice versa.

Abstract: A logic gate comprises a first switch, a second switch, a data network and a keeping circuitry. The first switch is adapted to connect a logic node to a first potential responsive to a transition of an enabling signal. The second switch is adapted to connect the logic node to a second potential via an electrical path responsive to a transition of the enabling signal. The data network is serially connected within the electrical path. The keeping circuitry comprises third and fourth switches serially connected between the logic node and the first potential and being controllable separately from each other, the third switch being adapted to be closed in case a potential on the logic node assumes the first potential and to be opened in case the potential on the logic node assumes the second potential.

Abstract: A masked ALU cell for a certain bit position p is provided. The cell comprises a base unit operable to generate a masked inverted carry out bit co*_n and an inverted masked sum bit s*_n based on a first masked output a*, a second masked output b*, and a re-masked carry bit input ci*; a transformation unit coupled to the base unit, the transformation unit having a first masked input bit aka, a second masked input bit bkb, a first mask input bit ka, a second mask input bit kb, a third mask input bit ks, and a fourth mask input bit kp, wherein the transformation unit is operable to generate the first masked output a* based on the first masked input bit aka, the first mask input bit ka, and the fourth mask input bit kp; the second masked output b* based on the second masked input bit bkb, the second mask input bit kb, and fourth mask input bit kp; and a masked sum bit sks based on the third mask input bit ks, the inverted masked sum bit s*_n, and the fourth mask input bit kp.

Abstract: A plurality of masked memory cells organized in at least two groups, each group using an individual mask signal, is operated by providing a logically valid mask signal only for a selected group comprising the memory cell to be accessed while a logically invalid mask signal are used for all groups other than the selected group.

Abstract: A logic gate comprises a first switch, a second switch, a data network and a keeping circuitry. The first switch is adapted to connect a logic node to a first potential responsive to a transition of an enabling signal. The second switch is adapted to connect the logic node to a second potential via an electrical path responsive to a transition of the enabling signal. The data network is serially connected within the electrical path. The keeping circuitry comprises third and fourth switches serially connected between the logic node and the first potential and being controllable separately from each other, the third switch being adapted to be closed in case a potential on the logic node assumes the first potential and to be opened in case the potential on the logic node assumes the second potential.

Abstract: Some embodiments show a digital fault detection circuit with an input circuit comprising an input and at least one output, wherein a first signal state at the input causes a predetermined signal state at the output and a second signal state at the input leaves the output floating. Moreover the digital fault detection circuit may comprise a signal line with a signal line input and a signal line output, wherein the signal line input is coupled to the output of the input circuit and furthermore a keeper circuit coupled to the signal line output and configured to keep the signal line at the predetermined signal state, after the signal state at the input has changed from the first signal state to the second signal state.

Abstract: Some embodiments show a storage circuit with fault detection. The storage circuit comprises, first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state.

Abstract: A macrocell including an adder block with a plurality of bit-slice adders, a bypass path and a control unit adapted to receive a carry of a first neighboring macrocell, and to output a carry by generation within the adder block or by passage of the carry of the first neighboring macrocell through the bypass path to a second neighboring macrocell. The control unit is adapted to signal a validity of the carry output of the macrocell depending on a logical combination of states of the two carry output lines. The control unit is further adapted, depending on a validity signal of the first neighboring macrocell indicating a validity of the carry, to prevent forwarding the carry.

Abstract: A macrocell including an adder block with a plurality of bit-slice adders, a bypass path and a control unit adapted to receive a carry of a first neighboring macrocell, and to output a carry by generation within the adder block or by passage of the carry of the first neighboring macrocell through the bypass path to a second neighboring macrocell. The control unit is adapted to signal a validity of the carry output of the macrocell depending on a logical combination of states of the two carry output lines. The control unit is further adapted, depending on a validity signal of the first neighboring macrocell indicating a validity of the carry, to prevent forwarding the carry.

Abstract: An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.