Abstract: Methods of fabricating fiber structures with embedded sensors are provided. The method includes obtaining a scaffold fiber and forming, by 1½-D printing using laser induced chemical vapor deposition, circuitry on the scaffold fiber to provide a fiber structure with embedded sensor. The forming includes printing a solid state oscillator about the scaffold fiber, and printing a sensing device about the scaffold fiber electrically coupled to the solid state oscillator to effect, at least in part, oscillations of the solid state oscillator. The forming further includes printing an antenna about the scaffold fiber electrically connected to the solid state oscillator to facilitate in operation wireless transmitting of a signal from the fiber structure with embedded sensor.

Abstract: Systems and methods for adjusting resistance on an exercise apparatus include a first resistance apparatus having an adjusting bracket, magnetic members mounted on an inner surface of the adjusting bracket, a stepper motor having an adjusting shaft and operable to traverse a portion of the length of the adjusting shaft. At a first position, the magnetic members are disposed above a flywheel, and in a second position, the magnetic members are disposed on opposite sides of the flywheel, providing resistance thereto. A load cell couples the adjusting bracket to the frame and generates a signal corresponding to the movement of the adjusting bracket. A computing system calculates resistance, rpms, power from load cell signal, stepper motor position, shaft rotational position and other sensor inputs.

Abstract: In some examples, a method comprises determining, at an electronic device having a first component of a first component type, a unique identifier associated with the first component. In some examples, in accordance with a determination that the unique identifier does not match the expected identifier of the component of the first component type in the electronic device, determining that the first component associated with the unique identifier satisfies one or more eligibility criteria. In some examples, in accordance with the determination that the first component associated with the unique identifier satisfies the one or more eligibility criteria, authenticating an association of the first component with the electronic device, including updating an installation counter associated with the first component, and updating the expected identifier for the component of the first type based on the unique identifier of the first component.

Abstract: Features from historical transaction and customer data of a financial institution are calculated and/or extracted. Each customer is assigned to a given profitability cluster within each interval of time over a historical period of time based on the corresponding features. A self-supervised machine learning model is trained on the features to predict the clusters in a future interval of time. Features for a most-recent past interval of time are provided as input to the model and the model returns a predicted cluster for a given customer in a future interval of time. When the customer-assigned cluster in the most-recent past interval of time is a higher prioritized cluster than the predicted cluster for the future interval of time, a system of a financial institution (FI) is notified to take one or more mitigating in an attempt to prevent customer churn with the FI.

Abstract: Techniques for machine learning assisted qubit state readout are disclosed. A system a set of training data that describes states of multiple qubits, and trains a neural network to determine qubit states based on the set of training data. The system obtains one or more unlabeled qubit signals, and determines one or more states corresponding to the unlabeled qubit signal(s), using the neural network. The unlabeled qubit signal(s) may include one or more multiplexed qubit signals, and the state(s) corresponding to the unlabeled qubit signal(s) may include one or more multi-qubit states based on the multiplexed qubit signal(s).

Abstract: One or more machine learning models are trained on financial institution (FI) specific customer and enterprise data to predict future transactions, churn likelihood, and a customer lifetime value (CLV) per customer of the FI over a given period of future time. In an embodiment, the CLV for the given period of future time is calculated and predicted using statistical and/or heuristic analysis based on predicted transactions provided by one or more models. The predicted transactions, churn likelihood, and CLV are provided through an Application Programming Interface (API) for integration into systems of the FI and/or accessible through a web-based interface and/or mobile application interface to users of the FI.

Abstract: A method, apparatus, and system for storing memory encryption realm key IDs is disclosed. A method comprises accessing a memory ownership table with a physical address to determine a realm ID associated with the physical address, accessing a key ID association structure with the realm ID to determine a realm key IS associated with the realm ID, and initiating a memory transaction based on the realm key ID. Once retrieved, the realm key ID may be stored in a translation lookaside buffer.

Abstract: An article includes an optical transforming layer and a guide region positioned inside and adjacent to at least a portion of a perimeter of the optical transforming layer. The guide region comprises an inlet end positioned adjacent to a first surface of the optical transforming layer and an outlet end positioned adjacent a second surface of the optical transforming layer. The guide region propagates light from the inlet end to the outlet end such that the light is directed from the first surface to the second surface. The guide region includes a phase-separated glass comprising a continuous network phase and a discontinuous phase. A relative difference in index of refraction between the continuous network phase and the discontinuous phase is greater than or equal to 0.3%. The discontinuous phase comprises elongated shaped regions aligned along a common axis and having an aspect ratio greater than or equal to 10:1.

Abstract: Methods of manufacturing a sheet or a board comprising recycled cellulose-containing materials, a binder composition comprising microfibrillated cellulose and one or more inorganic particulate material, and optionally one or more additive, wherein the sheet or board has an increased modulus of elasticity and modulus of rupture compared to a board prepared in a comparable method without microfibrillated cellulose, and to board, panel and construction products manufactured therefrom.

Abstract: Efficiently replacing software breakpoint instructions in processor-based devices is disclosed. In this regard, in one exemplary embodiment, a processor-based device is provided. The processor-based device comprises a system memory and a processor. The processor comprises a breakpoint slip register (BSR) configured to store an instruction of a software process that was replaced in the system memory by a software breakpoint instruction, and further comprises a breakpoint slip enable (BSE) indicator. The processor is configured to, during execution of the software process, execute the software breakpoint instruction. The processor is further configured to, responsive to executing the software breakpoint instruction, transfer program control to a debugger. The processor is also configured to, upon program control returning from the debugger, determine that the BSE indicator is set.

Abstract: Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system is disclosed. In disclosed examples, a dedicated in-memory TLB is supported in system memory for each process so that one process's cached page table entries do not displace another process's cached page table entries. When a process is scheduled to execute in a central processing unit (CPU), the in-memory TLB address stored for such process can be used by page table walker circuit in the CPU MMU to access the dedicated in-memory TLB for executing the process to perform VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB, the page table walker circuit can walk the page table in the MMU.

Abstract: Efficiently replacing software breakpoint instructions in processor-based devices is disclosed. In this regard, in one exemplary embodiment, a processor-based device is provided. The processor-based device comprises a system memory and a processor. The processor comprises a breakpoint slip register (BSR) configured to store an instruction of a software process that was replaced in the system memory by a software breakpoint instruction, and further comprises a breakpoint slip enable (BSE) indicator. The processor is configured to, during execution of the software process, execute the software breakpoint instruction. The processor is further configured to, responsive to executing the software breakpoint instruction, transfer program control to a debugger. The processor is also configured to, upon program control returning from the debugger, determine that the BSE indicator is set.

Abstract: Providing memory prefetch instructions with completion notifications in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based device provides a memory prefetch instruction that, when executed by a processor of a processor-based device, causes the processor to perform a memory prefetch operation by asynchronously retrieving a memory block from the system memory based on the memory address, and storing the memory block in a cache memory of the processor-based device. In response to completing the memory prefetch operation, the processor then notifies an executing software process that the memory prefetch operation is complete. Based on the notification, the executing software process may ensure that any subsequent memory access requests are not attempted until the memory prefetch operation is complete.

Abstract: Systems and methods for adjusting resistance on an exercise apparatus include a first resistance apparatus having an adjusting bracket, magnetic members mounted on an inner surface of the adjusting bracket, a stepper motor having an adjusting shaft and operable to traverse a portion of the length of the adjusting shaft. At a first position, the magnetic members are disposed above a flywheel, and in a second position, the magnetic members are disposed on opposite sides of the flywheel, providing resistance thereto. A load cell couples the adjusting bracket to the frame and generates a signal corresponding to the movement of the adjusting bracket. A computing system calculates resistance, rpms, power from load cell signal, stepper motor position, shaft rotational position and other sensor inputs.

Abstract: Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system is disclosed. In disclosed examples, a dedicated in-memory TLB is supported in system memory for each process so that one process's cached page table entries do not displace another process's cached page table entries. When a process is scheduled to execute in a central processing unit (CPU), the in-memory TLB address stored for such process can be used by page table walker circuit in the CPU MMU to access the dedicated in-memory TLB for executing the process to perform VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB, the page table walker circuit can walk the page table in the MMU.

Abstract: Tracking memory block access frequency in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that is configured to include an access count table for tracking accesses to memory blocks. The access count table is a packed table that comprises a plurality of access count values, each of which corresponds to a memory block of a plurality of memory blocks. Upon detecting a memory access operation (i.e., data-side operations such as memory load operations, memory store operations, atomic increment operations, set operations, and the like, or instruction-side operations such as code fetch operations) directed to a given memory block, the PE increments an access count value corresponding to the memory block. The access count value then can be accessed (e.g., by a process executing on the PE), and used to determine an access frequency for the memory block.

Abstract: A method, apparatus, and system for storing memory encryption realm key IDs is disclosed. A method comprises accessing a memory ownership table with a physical address to determine a realm ID associated with the physical address, accessing a key ID association structure with the realm ID to determine a realm key IS associated with the realm ID, and initiating a memory transaction based on the realm key ID. Once retrieved, the realm key ID may be stored in a translation lookaside buffer.

Abstract: Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Abstract: Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system is disclosed. In disclosed examples, a dedicated in-memory TLB is supported in system memory for each process so that one process's cached page table entries do not displace another process's cached page table entries. When a process is scheduled to execute in a central processing unit (CPU), the in-memory TLB address stored for such process can be used by page table walker circuit in the CPU MMU to access the dedicated in-memory TLB for executing the process to perform VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB, the page table walker circuit can walk the page table in the MMU.

Abstract: Systems and methods for adjusting resistance on an exercise apparatus include a first resistance apparatus having an adjusting bracket, magnetic members mounted on an inner surface of the adjusting bracket, a stepper motor having an adjusting shaft and operable to traverse a portion of the length of the adjusting shaft. At a first position, the magnetic members are disposed above a flywheel, and in a second position, the magnetic members are disposed on opposite sides of the flywheel, providing resistance thereto. A load cell couples the adjusting bracket to the frame and generates a signal corresponding to the movement of the adjusting bracket. A computing system calculates resistance, rpms, power from load cell signal, stepper motor position, shaft rotational position and other sensor inputs.