Abstract: Photosensitive lithium zinc aluminosilicate glasses that can be selectively irradiated and cerammed to provide patterned regions of glass and lithium-based glass ceramic, and composite glass articles made from such glasses and glass ceramics are provided. Compressive and tensile stress at the interface of the lithium-based glass-ceramic and lithium zinc aluminosilicate glass may be used to frustrate crack propagation in such a composite glass/glass ceramic article. Methods of making composite glass articles comprising such lithium-based glass ceramics and lithium zinc aluminosilicate glasses are also provided.

Abstract: Resistance mechanism and method for an exercise cycle includes an adjusting bracket having magnets mounted on its inner surface and spaced from a flywheel, an adjustment shaft having a threaded rod rotatably disposed through a tubular sleeve disposed on a frame and above the adjustment bracket, a threaded member mounted on the adjustment bracket and connected the threaded rod, and a linking assembly mounting the adjustment bracket to the frame, and including a first member, a first linking member, a first sensor, and a second sensor. The first sensor is disposed on the first member adjacent to the first end of the first linking member, a second sensor is disposed on the first linking member adjacent to the first sensor. A relative position of the first sensor and the second sensor is changed with respect to the corresponding movements of the adjusting bracket.

Abstract: Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Abstract: Treating main memory as a collection of tagged cache lines for trace logging. A computer system allocates a plurality of memory blocks, and a corresponding plurality of tags, within a main memory. Each tag indicates whether data stored in a corresponding memory block has been captured by an execution trace. The computer system synchronizes these tags with tags in a memory cache and manages a traced status of the memory blocks. This can include one or more of (i) setting a tag to indicate a memory block has not been captured based on identifying a direct memory access operation, (ii) setting a tag based on whether a paged-in value of a memory block has been captured, (iii) setting a tag or memory categorization based whether a memory block has been initialized, or (iv) setting a tag or memory categorization based whether a memory block is mapped to a file.

Abstract: Cache-based trace logging using tags in system memory. A processor influxes a cache line into a first cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in system memory and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line has been previously captured by a trace has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Abstract: Performing speculative address translation in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that defines a speculative translation instruction such as an enqueue instruction for offloading operations to a peripheral device. The speculative translation instruction references a plurality of bytes including one or more virtual memory addresses. After receiving the speculative translation instruction, an instruction decode stage of an execution pipeline circuit of the PE transmits a request for address translation of the virtual memory address to a memory management unit (MMU) of the PE. The MMU then performs speculative address translation of the virtual memory address into a corresponding translated memory address.

Abstract: Exemplary reach-based explicit dataflow processors and related computer-readable media and methods. The reach-based explicit dataflow processors are configured to support execution of producer instructions encoded with explicit naming of consumer instructions intended to consume the values produced by the producer instructions. The reach-based explicit dataflow processors are configured to make available produced values as inputs to explicitly named consumer instructions as a result of processing producer instructions. The reach-based explicit dataflow processors support execution of a producer instruction that explicitly names a consumer instruction based on using the producer instruction as a relative reference point from the producer instruction.

Abstract: An apparatus (1) and method for treating contaminated waste water (2). The apparatus comprises a heater (30), a feed apparatus (11, 12, 13, 14), for supplying contaminated waste water (2) to the heater (30) and a centrifuge (50, 60) downstream of the heater (30). A heat exchanger (20) is also provided which has a first channel (22) and a second channel (24). The first channel (22) is connected in a flow path extending between the feed apparatus (11, 12, 13, 14) and the centrifuge (50, 60); and a waste water outlet (9) from the main centrifuge (60) is fluidly coupled to an inlet of the second channel (24) of the heat exchanger (20).

Abstract: Enabling peripheral device messaging via application portals in processor-based devices is disclosed herein. In one embodiment, a processor-based device comprises a processing element (PE) including an application portal configured to logically operate as a message store, and that is exposed as an application portal address within an address space visible to a peripheral device that is communicatively coupled to the processor-based device. Upon receiving a message directed to the application portal address from the peripheral device, an application portal control circuit enqueues the message in the application portal. In some embodiments, the PE may further provide a dequeue instruction that may be executed as part of the application, and that results in a top element of the application portal being dequeued and transmitted to the application.

Abstract: Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system is disclosed. In disclosed examples, a dedicated in-memory TLB is supported in system memory for each process so that one process's cached page table entries do not displace another process's cached page table entries. When a process is scheduled to execute in a central processing unit (CPU), the in-memory TLB address stored for such process can be used by page table walker circuit in the CPU MMU to access the dedicated in-memory TLB for executing the process to perform VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB, the page table walker circuit can walk the page table in the MMU.

Abstract: Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Abstract: Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system is disclosed. In disclosed examples, a dedicated in-memory TLB is supported in system memory for each process so that one process's cached page table entries do not displace another process's cached page table entries. When a process is scheduled to execute in a central processing unit (CPU), the in-memory TLB address stored for such process can be used by page table walker circuit in the CPU MMU to access the dedicated in-memory TLB for executing the process to perform VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB, the page table walker circuit can walk the page table in the MMU.

Abstract: Disclosed are ticketed flow control mechanisms in a processing system with one or more masters and one or more slaves. In an aspect, a targeted slave receives a request from a requesting master. If the targeted slave is unavailable to service the request, a ticket for the request is provided to the requesting master. As resources in the targeted slave become available, messages are broadcasted for the requesting master to update the ticket value. When the ticket value has been updated to a final value, the requesting master may re-transmit the request.

Abstract: A system, method, and apparatus to provide mobility assistance to disabled persons. The invention includes a self-driving electric cart for transporting a blind or other disabled person along a pre-defined route defined by a path of magnetic markers. The magnetic markers interact through radio waves with a control mechanism on the cart. Utilizing the present invention, the blind person could touch a button on a pre-programmed control screen and ride safely in self-driving carts to any of several specific destinations, such as a job site, grocery store, relative's home, etc.

Abstract: Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Abstract: A method (500) and apparatus (50, 60) for lubrication of a gearbox (30) of an aircraft engine comprise provision (502) of oil to the gearbox (30) through a primary oil system (50) driven by a core (11) of the engine (10) in normal conditions; detection (504) of windmilling conditions and/or failure of the primary oil system (50); and in response to the detected condition or failure, activation (506) of an electric pump (61) of an auxiliary oil system (60), to provide oil to the gearbox (30).

Abstract: Providing express memory obsolescence in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based device provides a memory load instruction indicating a final memory load operation from a memory address (i.e., after the memory load operation represented by the memory load instruction is performed, the value at the memory address need not be maintained). Upon receiving the memory load instruction by an execution pipeline of the processor-based device, an entry corresponding to the memory address of the memory load instruction is located in an intermediate memory external to the system memory of the processor-based device, and used to perform the final memory load operation. After the final memory load operation is performed using the entry, a value of an obsolete indicator for the entry is set to indicate that the entry can be reused prior to its contents being written to the system memory.

Abstract: Performing atomic store-and-invalidate operations in processor-based devices is disclosed. In this regard, a processing element (PE) of one or more PEs of a processor-based device includes a store-and-invalidate logic circuit used by a memory access stage of an execution pipeline of the PE to perform an atomic store-and-invalidate operation. Upon receiving an indication to perform a store-and-invalidate operation (e.g., in response to a store-and-invalidate instruction execution) comprising a store address and store data, the memory access stage uses the store-and-invalidate logic circuit to write the store data to a memory location indicated by the store address, and to invalidate an instruction cache line corresponding to the store address in an instruction cache of the PE.

Abstract: An aircraft engine having an oil circuit and a transmission that can be supplied with oil via the oil circuit. Oil fed to the transmission can be directed out of the transmission into an oil reservoir, from which oil can be introduced directly back into the transmission via a hydraulic line path. According to the invention, the oil fed to the oil reservoir can only be fed to the hydraulic line path below a defined filling level of the oil reservoir. When the defined filling level of the oil reservoir is reached, oil can also be introduced into a further hydraulic line path.

Abstract: A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation lookaside buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.