Abstract: A method, apparatus, and system for storing memory encryption realm key IDs is disclosed. A method comprises accessing a memory ownership table with a physical address to determine a realm ID associated with the physical address, accessing a key ID association structure with the realm ID to determine a realm key IS associated with the realm ID, and initiating a memory transaction based on the realm key ID. Once retrieved, the realm key ID may be stored in a translation lookaside buffer.

Abstract: Performing speculative address translation in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that defines a speculative translation instruction such as an enqueue instruction for offloading operations to a peripheral device. The speculative translation instruction references a plurality of bytes including one or more virtual memory addresses. After receiving the speculative translation instruction, an instruction decode stage of an execution pipeline circuit of the PE transmits a request for address translation of the virtual memory address to a memory management unit (MMU) of the PE. The MMU then performs speculative address translation of the virtual memory address into a corresponding translated memory address.

Abstract: In some examples, a method comprises determining, at an electronic device having a first component of a first component type, a unique identifier associated with the first component. In some examples, in accordance with a determination that the unique identifier does not match the expected identifier of the component of the first component type in the electronic device, determining that the first component associated with the unique identifier satisfies one or more eligibility criteria. In some examples, in accordance with the determination that the first component associated with the unique identifier satisfies the one or more eligibility criteria, authenticating an association of the first component with the electronic device, including updating an installation counter associated with the first component, and updating the expected identifier for the component of the first type based on the unique identifier of the first component.

Abstract: Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Abstract: The hand washing assembly includes a hood defining a cavity within the hood, a valve structure located at least partially within the cavity, and a lever handle. The lever handle is operatively coupled to the valve structure and configured to move the valve structure between a first position in which the valve structure prevents a flow of fluid through the valve structure and a second position in which the valve structure permits the flow of fluid through the valve structure. The lever handle includes a contact surface positioned within the cavity and configured to move toward a top wall of the hood as the valve structure moves into the second position and configured to move away from the top wall as the valve structure moves into the first position.

Abstract: Tracking memory block access frequency in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that is configured to include an access count table for tracking accesses to memory blocks. The access count table is a packed table that comprises a plurality of access count values, each of which corresponds to a memory block of a plurality of memory blocks. Upon detecting a memory access operation (i.e., data-side operations such as memory load operations, memory store operations, atomic increment operations , set operations, and the like, or instruction-side operations such as code fetch operations) directed to a given memory block, the PE increments an access count value corresponding to the memory block. The access count value then can be accessed (e.g., by a process executing on the PE), and used to determine an access frequency for the memory block.

Abstract: An improved bio-electrochemical wastewater treatment process and system (1) is disclosed. An electrode assembly (4) is defined by interconnecting a set of electrode modules (5). Each electrode module (5) has a first electrode of an anode-cathode pair coated with electrogenic microbes adapted to generate electrons via the consumption of organic matter in wastewater. An electrode module (5) has a second electrode of the anode-cathode pair, and a body, supporting and separating the first and second electrodes. Each electrode module (5) also comprises an interface for physically connecting the module with at least one other of the set.

Abstract: In some examples, a method comprises determining, at an electronic device having a first component of a first component type, a unique identifier associated with the first component. In some examples, in accordance with a determination that the unique identifier does not match the expected identifier of the component of the first component type in the electronic device, determining that the first component associated with the unique identifier satisfies one or more eligibility criteria. In some examples, in accordance with the determination that the first component associated with the unique identifier satisfies the one or more eligibility criteria, authenticating an association of the first component with the electronic device, including updating an installation counter associated with the first component, and updating the expected identifier for the component of the first type based on the unique identifier of the first component.

Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

Abstract: A log splitter includes a chassis having a support table configured to support a log to be split, a splitter screw having a generally conical shape and mounted to a rotatable screw shaft that is supported by the chassis, and a drive assembly configured to rotate the shaft to impart rotational movement to the splitter screw about a screw axis. The drive assembly includes a motor coupled to the screw shaft via a constant velocity transmission (CVT) (also known as continuously variable transmission). The CVT can provide both high speed and high torque during the splitting process as required to split the log. A fall restriction bar helps restrict a person from accidentally falling onto the splitter screw. An engine-kill bar is pivotally mounted to the chassis. A log-rotation stop mechanism is configured to restrict rotation of a log that gets stuck on the splitter screw.

Abstract: A handwashing valve structure includes a mounting structure, a dispensing structure, and a control structure. The mounting structure is configured to attach to a liquid vessel. The dispensing structure is configured to dispense a liquid from the liquid vessel and is movable between a closed position and an open position. The control structure is configured to move the dispensing structure between the closed position and the open position. The control structure is configured to be moved by pressure from a portion of a user's body to move the dispensing structure from the closed position to the open position. The dispensing structure is configured to automatically move from the open position to the closed position in the absence of any pressure from the portion of the user's body onto the control structure.

Abstract: Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Abstract: Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Abstract: The present invention relates to a perfusion bioreactor for co-culturing, wherein the bioreactor grows cells in two separate environments and enables communication across environments and populations. The chambers' contents are continuously mixed to expose the environment (or cell population) of each chamber to the secreted products of the other chamber. The said bioreactor comprises at least, but not limited to, two chambers, with separate cell populations with at least two separate environments independently selected from aerobic or anaerobic environment and media favorable to cell growth. The bioreactor allows for multiple samples to be collected during an experiment to enable various analytical techniques and results. Additionally, the bioreactor comprises a multi-chamber cell culture system capable of emulating the gastro-intestinal tract.

Abstract: An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.

Abstract: Methods of fabricating fiber structures with embedded sensors are provided. The method includes obtaining a scaffold fiber and forming, by 1½-D printing using laser induced chemical vapor deposition, circuitry on the scaffold fiber to provide a fiber structure with embedded sensor. The forming includes printing a solid state oscillator about the scaffold fiber, and printing a sensing device about the scaffold fiber electrically coupled to the solid state oscillator to effect, at least in part, oscillations of the solid state oscillator. The forming further includes printing an antenna about the scaffold fiber electrically connected to the solid state oscillator to facilitate in operation wireless transmitting of a signal from the fiber structure with embedded sensor.

Abstract: An article includes an optical transforming layer and a guide region positioned inside and adjacent to at least a portion of a perimeter of the optical transforming layer. The guide region comprises an inlet end positioned adjacent to a first surface of the optical transforming layer and an outlet end positioned adjacent a second surface of the optical transforming layer. The guide region propagates light from the inlet end to the outlet end such that the light is directed from the first surface to the second surface. The guide region includes a phase-separated glass comprising a continuous network phase and a discontinuous phase. A relative difference in index of refraction between the continuous network phase and the discontinuous phase is greater than or equal to 0.3%. The discontinuous phase comprises elongated shaped regions aligned along a common axis and having an aspect ratio greater than or equal to 10:1.

Abstract: Photosensitive lithium zinc aluminosilicate glasses that can be selectively irradiated and cerammed to provide patterned regions of glass and lithium-based glass ceramic, and composite glass articles made from such glasses and glass ceramics are provided. The lithium zinc aluminosilicate glass can be negatively photosensitive or positively photosensitive to radiation having a wavelength in a range from about 248 nm to about 360 nm.

Abstract: A processor supporting a translation lookaside buffer (TLB) modification instruction for updating a hardware-managed TLB is disclosed. A page table (PT) entry (PTE) corresponding to a virtual memory address is identified by a PT walking circuit walking the PT and a corresponding TLB entry is created. An execution circuit in the processor executes a TLB modification instruction to cause the TLB entry corresponding to the virtual memory address to be updated based on an update to the PT mapping information in the PTE corresponding to the virtual memory address. In one example, a portion of the PT mapping information in a PTE corresponding to a virtual memory address is stored in a TLB mapping information in a TLB entry corresponding to the virtual memory address in response to the TLB modification instruction being executed by the execution circuit without invalidating the TLB entry.