Abstract: A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.

Abstract: Selective honoring of speculative memory-prefetch requests based on bandwidth constraint of a memory access path component(s) in a processor-based system. To reduce memory access latency, a CPU includes a request size in a memory read request of requested data to be read from memory and a request mode of the requested data as required or preferred. A memory access path component includes a memory read honor circuit configured to receive the memory read request and consult the request size and request mode of requested data in the memory read request. If the selective prefetch data honor circuit determines that bandwidth of the memory system is less than a defined bandwidth constraint threshold, then the memory read request is forwarded to be fulfilled, otherwise, the memory read request is downgraded to only include any requested required data.

Abstract: An oven appliance includes a cabinet extending between a top portion and a bottom portion along a vertical direction and extending between a left side and a right side along a lateral direction. The vertical direction and the lateral direction are mutually perpendicular. The oven appliance also includes a maintop having a heating element positioned within the maintop. The maintop is fixedly mounted to the top portion of the cabinet. The maintop is constrained against movement along the lateral direction by a first emboss at the left side of the cabinet and a second emboss at the right side of the cabinet.

Abstract: Exemplary reach-based explicit dataflow processors and related computer-readable media and methods. The reach-based explicit dataflow processors are configured to support execution of producer instructions encoded with explicit naming of consumer instructions intended to consume the values produced by the producer instructions. The reach-based explicit dataflow processors are configured to make available produced values as inputs to explicitly named consumer instructions as a result of processing producer instructions. The reach-based explicit dataflow processors support execution of a producer instruction that explicitly names a consumer instruction based on using the producer instruction as a relative reference point from the producer instruction.

Abstract: Disclosed are ticketed flow control mechanisms in a processing system with one or more masters and one or more slaves. In an aspect, a targeted slave receives a request from a requesting master. If the targeted slave is unavailable to service the request, a ticket for the request is provided to the requesting master. As resources in the targeted slave become available, messages are broadcasted for the requesting master to update the ticket value. When the ticket value has been updated to a final value, the requesting master may re-transmit the request.

Abstract: Photosensitive lithium zinc aluminosilicate glasses that can be selectively irradiated and cerammed to provide patterned regions of glass and lithium-based glass ceramic, and composite glass articles made from such glasses and glass ceramics are provided. Compressive and tensile stress at the interface of the lithium-based glass-ceramic and lithium zinc aluminosilicate glass may be used to frustrate crack propagation in such a composite glass/glass ceramic article. Methods of making composite glass articles comprising such lithium-based glass ceramics and lithium zinc aluminosilicate glasses are also provided.

Abstract: Photosensitive lithium zinc aluminosilicate glasses that can be selectively irradiated and cerammed to provide patterned regions of glass and lithium-based glass ceramic, and composite glass articles made from such glasses and glass ceramics are provided. Compressive and tensile stress at the interface of the lithium-based glass-ceramic and lithium zinc aluminosilicate glass may be used to frustrate crack propagation in such a composite glass/glass ceramic article. Methods of making composite glass articles comprising such lithium-based glass ceramics and lithium zinc aluminosilicate glasses are also provided.

Abstract: A photochromic glass that includes a base glass and a photochromic agent is described. The base glass is a modified boroaluminosilicate glass and the photochromic agent is a nanocrystalline cuprous halide phase. The photochromic glass exhibits a sharp cutoff in the UV or short wavelength visible portion of the spectrum along with an absorption band at longer wavelengths in the visible. The nanocrystalline cuprous halide phase includes Cu2+, which provides states within the bandgap of the cuprous halide that permit the glass to absorb visible light. Absorption of visible light drives a photochromic transition without compromising the sharp cutoff. The nanocrystalline cuprous halide phase may optionally include Ag.

Abstract: An isolated or synthesized compound of Formula I and salts thereof are provided. A compound isolated from Actinomadura and having a chemical formula of C38H60O12 is also provided. Compositions including the compounds and methods of using the compounds to treat bacterial infections including gram positive infections such as C. difficile are also disclosed.

Abstract: The disclosure is directed to broadband, glass optical polarizers and to methods for making the glass optical polarizers. The glass optical polarizer includes a substantially bubble free fusion drawn glass having two pristine glass surfaces and a plurality of elongated zero valent metallic particle polarizing layers.

Abstract: A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation lookaside buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.

Abstract: An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.

Abstract: A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.

Abstract: Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.

Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

Abstract: A method, apparatus, and system for storing memory encryption realm key IDs is disclosed. A method comprises accessing a memory ownership table with a physical address to determine a realm ID associated with the physical address, accessing a key ID association structure with the realm ID to determine a realm key IS associated with the realm ID, and initiating a memory transaction based on the realm key ID. Once retrieved, the realm key ID may be stored in a translation lookaside buffer.

Abstract: Adaptively predicting usefulness of prefetches generated by hardware prefetch engines of processor-based devices is disclosed. In this regard, a processor-based device provides a hardware prefetch engine including a sampler circuit and a predictor circuit. The sampler circuit stores data related to demand requests and prefetch requests directed to memory addresses corresponding to a subset of sets of a cache of the processor-based device. The predictor circuit includes a plurality of confidence counters that correspond to the memory addresses tracked by the sampler circuit, and that indicate a level of confidence in the usefulness of the corresponding memory addresses. The confidence counters provided by the predictor circuit are trained in response to demand request hits and misses (and, in some aspects, prefetch misses) on the memory addresses tracked by the sampler circuit. The predictor circuit may then use the confidence counters to generate usefulness predictions for subsequent prefetch requests.

Abstract: A mobile insurance architecture includes a wireless communication interface that connects mobile client devices to wireless networks. An insurance server cluster that includes a group of independent network servers operates and appears to mobile client devices as if the group of independent network servers were a single computer server. An adaptive transmission controller communicates with the insurance server cluster and processes content in multiple mobile formats that may be optimized to the screen sizes of the mobile client devices. The insurance server cluster responds to native application clients resident to the mobile client devices. The native application clients contain code stored on a non-transitory media that render insurance quoting services, insurance claims services, on-line insurance policy services, usage based insurance services, mobile monitoring services, or insurance agency management services.

Abstract: A method for displaying archived exercise classes comprising displaying information about archived exercise classes that can be accessed by a first user via a computer network on a display screen at a first location, wherein the first user can select among a plurality of archived classes, outputting digital video and audio content comprising the selected archived class, detecting a performance parameter for the first user at a particular point in the selected class, displaying the performance parameter on the display screen, and displaying performance parameters from a second user at a second location on the display screen such that at least one of the performance parameters from the first user and at least one of the performance parameters from the second user at the same point in the class are presented for comparison.

Abstract: A method (500) and apparatus (50, 60) for lubrication of a gearbox (30) of an aircraft engine comprise provision (502) of oil to the gearbox (30) through a primary oil system (50) driven by a core (11) of the engine (10) in normal conditions; detection (504) of windmilling conditions and/or failure of the primary oil system (50); and in response to the detected condition or failure, activation (506) of an electric pump (61) of an auxiliary oil system (60), to provide oil to the gearbox (30).