Patents by Inventor Thomas Philip

Thomas Philip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8678132
    Abstract: An exhaust system includes a muffler, an inlet pipe, and an exhaust pipe. The muffler includes an inlet hole adapted to receive the inlet pipe and an outlet hole to receive the exhaust pipe. The inlet pipe has a first and second linear portions extending from a radiused portion, the first and second linear portions being generally perpendicular to one another. The radiused portion and the first linear portion of the inlet pipe are positioned within the muffler. Portions of the inlet pipe and exhaust pipe located within the muffler may optionally include perforations and be closed off.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: March 25, 2014
    Assignee: Catalytic Combustion Corporation
    Inventors: Randall Joseph Bischel, Thomas Philip King
  • Publication number: 20140079807
    Abstract: The disclosure is directed to glass compositions that incorporate copper into an otherwise homogeneous glass and to a method for making such glass. This incorporation of the copper into the glass composition imparts significant antimicrobial activity to the glass. A method of making a copper-containing glass article comprises: batching a glass batch comprising: 40-85 SiO2; 10-40 B2O3; 1-19 Al2O3; 0.1-20 CuO or a selected salt of Cu that is convertible into CuO during melting; 0-20 M2O, wherein M is Li, Na, K, or combinations thereof; 0-25 RO, wherein R is Ca, Sr, Mg, or combinations thereof; and 0-20 ZnO. melting the batch to form a melted glass; and forming the melted glass to form the copper-containing glass article having antimicrobial properties.
    Type: Application
    Filed: March 27, 2012
    Publication date: March 20, 2014
    Inventors: Nicholas Francis Borrelli, Odessa Natalie Petzold, Joseph Francis Schroeder, Thomas Philip Seward, Florence Verrier, Ying Wei
  • Publication number: 20140038781
    Abstract: A method for providing cycling classes to remote users comprising providing information about available cycling classes that can be accessed via a digital communication network by a user at a remote location for display at the remote location, receiving from the user a selection of one of the available cycling classes for display at the remote location, and sending digital video and audio content comprising the selected cycling class from a server to a computer associated with a stationary bike at the remote location for display to the user on a display screen associated with the stationary bike. In various exemplary embodiments, the digital and audio content sent to the computer associated with the stationary bike is streamed for display to the user in substantially in real-time. In various exemplary embodiments, the digital and audio content sent to the computer associated with the stationary bike is archived content provided from a database.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 6, 2014
    Inventors: John Paul Foley, Thomas Philip Cortest, Yu Feng, Christopher Brett Sira, Hans Schlichting Woolley
  • Publication number: 20130337123
    Abstract: An instant coffee composition is provided having soluble coffee particles. The particles have internal pores, and at least some of the internal pores contain a pressurized gas. Further, the soluble coffee particles are provided with finely-ground insoluble coffee material on an outer surface of the soluble coffee particles. A method of forming the instant coffee composition, a container for the composition, and a beverage dispensing system are also provided.
    Type: Application
    Filed: December 14, 2011
    Publication date: December 19, 2013
    Inventors: Ian Denis Fisk, Thomas Philip Irnison, Bary Zeller
  • Patent number: 8612690
    Abstract: Embodiments of a data cache are disclosed that substantially decrease a number of accesses to a physically-tagged tag array of the data cache are provided. In general, the data cache includes a data array that stores data elements, a physically-tagged tag array, and a virtually-tagged tag array. In one embodiment, the virtually-tagged tag array receives a virtual address. If there is a match for the virtual address in the virtually-tagged tag array, the virtually-tagged tag array outputs, to the data array, a way stored in the virtually-tagged tag array for the virtual address. In addition, in one embodiment, the virtually-tagged tag array disables the physically-tagged tag array. Using the way output by the virtually-tagged tag array, a desired data element in the data array is addressed.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: December 17, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Robert D. Clancy, James Norris Dieffenderfer, Thomas Philip Speier
  • Publication number: 20130293372
    Abstract: A monitoring service is described that allows flexible response through operators taken from a group of chosen individuals. When an alarm state is triggered the chosen individuals may act collaboratively as operators to manage alarm conditions for a particular user.
    Type: Application
    Filed: March 29, 2013
    Publication date: November 7, 2013
    Inventors: Thomas Philip, Geoffrey Vanderkooy
  • Publication number: 20130204645
    Abstract: A mobile insurance architecture includes a wireless communication interface that connects mobile client devices to wireless networks. An insurance server cluster that includes a group of independent network servers operates and appears to mobile client devices as if the group of independent network servers were a single computer server. An adaptive transmission controller communicates with the insurance server cluster and processes content in multiple mobile formats that may be optimized to the screen sizes of the mobile client devices. The insurance server cluster responds to native application clients resident to the mobile client devices. The native application clients contain code stored on a non-transitory media that render insurance quoting services, insurance claims services, on-line insurance policy services, usage based insurance services, mobile monitoring services, or insurance agency management services.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 8, 2013
    Applicant: Progressive Casualty Insurance Company
    Inventors: Matthew Daniel Lehman, Bradley Thomas Philips, Pawan Kumar Divakarla, Toby Kramer Alfred, William Curtis Everett, Brian Joseph Surtz, Raymond Scott Ling
  • Patent number: 8499208
    Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: July 30, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: James Norris Dieffenderfer, Anand Krishnamurthy, Clint Wayne Mumford, Jason Lawrence Panavich, Ketan Vitthal Patel, Ravi Rajagopalan, Thomas Philip Speier
  • Publication number: 20130191559
    Abstract: The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.
    Type: Application
    Filed: April 19, 2012
    Publication date: July 25, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Robert D. Clancy, Thomas Philip Speier, James Norris Dieffenderfer
  • Publication number: 20130185520
    Abstract: Apparatuses and related systems and methods for determining cache hit/miss of aliased addresses in virtually-tagged cache(s) are disclosed. In one embodiment, virtual aliasing cache hit/miss detector for a VIVT cache is provided. The detector comprises a TLB configured to receive a first virtual address and a second virtual address from the VIVT cache resulting from an indexed read into the VIVT cache based on the first virtual address. The TLB is further configured to generate first and second physical addresses translated from the first and second virtual addresses, respectively, The detector further comprises a comparator configured to receive the first and second physical addresses and effectuate a generation of an aliased cache hit/miss indicator based on a comparison of the first and second physical addresses. In this manner, the virtual aliasing cache hit/miss detector correctly generates cache hits and cache misses, even in the presence of aliased addressing.
    Type: Application
    Filed: May 23, 2012
    Publication date: July 18, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: James Norris Dieffenderfer, Robert D. Clancy, Thomas Philip Speier
  • Publication number: 20130185473
    Abstract: Embodiments of a data cache are disclosed that substantially decrease a number of accesses to a physically-tagged tag array of the data cache are provided. In general, the data cache includes a data array that stores data elements, a physically-tagged tag array, and a virtually-tagged tag array. In one embodiment, the virtually-tagged tag array receives a virtual address. If there is a match for the virtual address in the virtually-tagged tag array, the virtually-tagged tag array outputs, to the data array, a way stored in the virtually-tagged tag array for the virtual address. In addition, in one embodiment, the virtually-tagged tag array disables the physically-tagged tag array. Using the way output by the virtually-tagged tag array, a desired data element in the data array is addressed.
    Type: Application
    Filed: March 22, 2012
    Publication date: July 18, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Robert D. Clancy, James Norris Dieffenderfer, Thomas Philip Speier
  • Publication number: 20130151799
    Abstract: Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 13, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Jason Lawrence Panavich, James Norris Dieffenderfer, Thomas Andrew Sartorius, Thomas Philip Speier
  • Patent number: 8443162
    Abstract: Techniques for controllably allocating a portion of a plurality of memory banks as cache memory are disclosed. To this end, a configuration tracker and a bank selector are employed. The configuration tracker configures whether each memory bank is to operate in a cache or not. The bank selector has a plurality of bank distributing functions. Upon receiving an incoming address, the bank selector determines the configuration of memory banks currently operating as the cache and applies an appropriate bank distributing function based on the configuration of memory banks. The applied bank distributing function utilizes bits in the incoming address to access one of the banks configured as being in the cache.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: May 14, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Philip Speier, James Norris Dieffenderfer, Ravi Rajagopalan
  • Patent number: 8386716
    Abstract: Techniques and methods are used to control allocations of cache lines to a higher level cache that have been displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby the displaced cache line castouts are not allocated to the higher level cache. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: February 26, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Philip Speier, James Norris Dieffenderfer, Thomas Andrew Sartorius
  • Patent number: 8352682
    Abstract: Efficient techniques are described for enforcing order of memory accesses. A memory access request is received from a device which is not configured to generate memory barrier commands. A surrogate barrier is generated in response to the memory access request. A memory access request may be a read request. In the case of a memory write request, the surrogate barrier is generated before the write request is processed. The surrogate barrier may also be generated in response to a memory read request conditional on a preceding write request to the same address as the read request. Coherency is enforced within a hierarchical memory system as if a memory barrier command was received from the device which does not produce memory barrier commands.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: January 8, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Philip Speier, James Norris Dieffenderfer, Thomas Andrew Sartorius
  • Publication number: 20120330016
    Abstract: A novel bidentate ligand of general formula (I) is described together with a process for the carbonylation of ethylenically unsaturated compounds. The group X1 may be defined as a univalent hydrocarbyl radical of up to 30 atoms containing at least one nitrogen atom having a pKb in dilute aqueous solution at 18° C. of between 4 and 14 wherein the said at least one nitrogen atom is separated from the Q2 atom by between 1 and 3 carbon atoms. The group X2 is defined as X1, X3 or X4 or represents a univalent radical of up to 30 atoms having at least one primary, secondary or aromatic ring carbon atom wherein each said univalent radical is joined via said at least one primary, secondary or aromatic ring carbon atom(s) respectively to the respective atom Q2. Q1 and Q2 each independently represent phosphorus, arsenic or antimony.
    Type: Application
    Filed: December 29, 2010
    Publication date: December 27, 2012
    Applicant: LUCITE INTERNATIONAL UK LIMITED
    Inventors: Graham Ronald Eastham, Mark Waugh, Paul Pringle, Thomas Philip William Turner
  • Publication number: 20120114825
    Abstract: A method of forming an agglomerated foaming coffee composition, the method comprising the step of agglomerating a coffee composition, the majority of the coffee composition by weight consisting of particles of foaming soluble coffee, wherein at least some of the particles of foaming soluble coffee have not been milled prior to their agglomeration.
    Type: Application
    Filed: April 6, 2010
    Publication date: May 10, 2012
    Inventor: Thomas Philip Imison
  • Publication number: 20120059995
    Abstract: Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are reduced. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.
    Type: Application
    Filed: November 9, 2011
    Publication date: March 8, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Thomas Philip Speier, James Norris Dieffenderfer, Thomas Andrew Sartorius
  • Patent number: 8078803
    Abstract: Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: December 13, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Philip Speier, James Norris Dieffenderfer, Thomas Andrew Sartorius
  • Publication number: 20110202727
    Abstract: Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are reduced. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache or the selected line is a write-through line. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.
    Type: Application
    Filed: February 18, 2010
    Publication date: August 18, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventors: Thomas Philip Speier, James Norris Dieffenderfer, Thomas Andrew Sartorius