Abstract: Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.

Abstract: The present invention provides a foaming instant coffee composition comprising particles having a bulk density of from 0.16 to 0.45 g/cm3, said particles comprising a continuous phase comprising an instant coffee matrix and a non-continuous phase comprising particles of a foamable component containing a gas.

Abstract: The invention is a dosing pump that can be worn on the body of a patient for subcutaneously delivering liquid with centi-micro liter accuracy to his/her body. The dosing pump comprises a pump unit, an internal control unit; and a reservoir containing the liquid. The pump unit comprises a pump block (12) comprising a pump chamber (118) with a pump diaphragm (107) stretched across its entrance and a pump pin cylinder (110) extending from the exterior of the pump block to the entrance to the pump chamber; a pump pin (20) that is located in the pump pin cylinder and a motor unit comprising a motor and gear system. When the motor is activated, the rotational motion of the motor and the gears in the gear system is transformed into cyclic back and forth linear motion of the pump pin in the pin cylinder pumping the liquid from the reservoir into the patient.

Abstract: The present invention relates to chalcone and chalcone derivatives and analogs which are useful as angiogenesis inhibitors. The present compounds, which are inexpensive to synthesize, exhibit unexpectedly good activity as angiogenesis inhibitors. The present invention also relates to the use of chalcone and its analogs as antitumor/anticancer agents and to treat a number of conditions or disease states in which angiogenesis is a factor, including angiogenic skin diseases such as psoriasis, acne, rosacea, warts, eczema, hemangiomas, lymphangiogenesis, among numerous others, as well as chronic inflammatory disease such as arthritis.

Abstract: Efficient techniques are described for enforcing order of memory accesses. A memory access request is received from a device which is not configured to generate memory barrier commands. A surrogate barrier is generated in response to the memory access request. A memory access request may be a read request. In the case of a memory write request, the surrogate barrier is generated before the write request is processed. The surrogate barrier may also be generated in response to a memory read request conditional on a preceding write request to the same address as the read request. Coherency is enforced within a hierarchical memory system as if a memory barrier command was received from the device which does not produce memory barrier commands.

Abstract: Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

Abstract: A processing system and method of communicating within the processing system is disclosed. The processing system may include a bus; a memory region coupled to the bus; and a plurality of processing components having access to the memory region over the bus, each of the processing components being configured to perform a semaphore operation to gain access to the memory region by simultaneously requesting a read operation and a write operation to a semaphore location over the bus.

Abstract: A foaming freeze-dried instant coffee composition comprising particles having a bulk density of from 0.19 to 0.25 g/cm3 and a closed pore volume of at least 0.05 ml/g, said particles comprising a freeze-dried instant coffee matrix having entrapped therein particles of a foamable component having closed pores containing a gas.

Abstract: Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

Abstract: The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus interconnect is configured to interface the processors to the memory devices. The bus interconnect is further configured to enforce an ordering constraint for a strongly-ordered memory access request from an originating processor to a target memory device by sending a memory barrier to each of the other memory devices accessible by the originating processor, except for those memory devices that the bus interconnect can confirm have no unexecuted memory access requests from the originating processor.

Abstract: A shell (1) for a drum comprises an outer layer (1a), an intermediate layer (1b) and inner layer (1c), wherein the intermediate layer has a plurality of larger apertures (2) and the inner layer has a plurality of smaller apertures (3) overlying the larger apertures.

Abstract: The present invention relates to chalcone and chalcone derivatives and analogs which are useful as angiogenesis inhibitors. The present compounds, which are inexpensive to synthesize, exhibit unexpectedly good activity as angiogenesis inhibitors. The present invention also relates to the use of chalcone and its analogs as antitumor/anticancer agents and to treat a number of conditions or disease states in which angiogenesis is a factor, including angiogenic skin diseases such as psoriasis, acne, rosacea, warts, eczema, hemangiomas, lymphangiogenesis, among numerous others, as well as chronic inflammatory disease such as arthritis.

Abstract: A catalytically active glass-ceramic and method for producing a catalytically active multi-phase glass-ceramic in which at least one catalyst precursor is mixed with a glass-ceramic precursor formulation to form a catalyst precursor/glass-ceramic precursor mixture. The catalyst precursor/glass-ceramic precursor mixture is then melted to form an amorphous glass material which, in turn, is devitrified to form a polycrystalline ceramic. The polycrystalline ceramic is then activated, forming a catalytically active multi-phase glass-ceramic.

Abstract: Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

Abstract: The present invention relates to chalcone and chalcone derivatives and analogs which are useful as angiogenesis inhibitors. The present compounds, which are inexpensive to synthesize, exhibit unexpectedly good activity as angiogenesis inhibitors. The present invention also relates to the use of chalcone and its analogs as antitumor/anticancer agents and to treat a number of conditions or disease states in which angiogenesis is a factor, including angiongenic skin diseases such as psoriasis, acne, rosacea, warts, eczema, hemangiomas, lymphangiogenesis, among numerous others, as well as chronic inflammatory disease such as arthritis.

Abstract: Semaphore operation manages exclusive access to a memory that is shared by a plurality of processing elements. Semaphore reservation status for exclusive access by a processing element is monitored by a memory controller. To clear an obsolete reservation status, a command signal is transmitted for a write operation to the memory while prohibiting update of the contents of a memory. The reservation status at the controller is changed from a reservation state to a non-reservation state in response to receipt of the command signal.

Abstract: Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. When it is determined that displaced lines have already been allocated in a higher level, the allocations of the displaced cache lines are prevented in the next level cache, thus, reducing castouts. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.

Abstract: A foaming composition is provided comprising a particulate ingredient having a plurality of internal voids containing entrapped supercritical fluid having a critical temperature of at least about 10° C. Additionally, a method is provided for preparing such a foaming composition. A supercritical fluid having a critical temperature of at least about 10° C. is contacted with a particulate ingredient having a glass transition temperature above ambient temperature at a temperature above the glass transition temperature of the particulate ingredient, wherein the particulate ingredient comprises a plurality of internal voids. The particulate ingredient is held at the temperature above the glass transition temperature of the particulate ingredient for a period of time effective to allow transfer of the supercritical fluid into the plurality of internal voids of the particulate ingredient.

Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.

Abstract: During a Built-In Self-Test (BIST) routine, execution of a sequence of tests is re-initiated after a corrective action is taken starting with the test having the highest re-ordered priority. The test having the highest re-ordered priority corresponds to a test in a sequence of tests that detected the error corresponding to the corrective action taken or a related test in the case where the test that detected the error is dependent upon results generated by the related test. According to one embodiment, a BIST routine is executed by initiating execution of a sequence of tests configured to detect errors and, after a corrective action is taken in response to one or more of the errors being detected, re-initiating execution of the sequence of tests starting with the test that detected the error corresponding to the corrective action most recently taken.