Patents by Inventor Thomas Scott Morris

Thomas Scott Morris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230402333
    Abstract: A system in package (SiP) with an air cavity is disclosed. In one aspect, a technique to bond a lid over the air cavity that reduces the risk of cavity integrity failure is provided. More specifically, an epoxy seal is created on four walls of a lid enclosing the cavity. A further sputtered metal layer is added over the epoxy seal to provide additional structural rigidity, electromagnetic emission suppression and to assist in preventing leaks through the epoxy seal.
    Type: Application
    Filed: May 16, 2023
    Publication date: December 14, 2023
    Inventors: MD Hasnine, Christine Blair, Thomas Scott Morris, Neftali Salazar
  • Patent number: 11765826
    Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: September 19, 2023
    Assignee: Qorvo US, Inc.
    Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
  • Publication number: 20230247814
    Abstract: The disclosure relates to a shielded electronic module which includes a module shielding structure and an electronic module with an interposer, a shielded electronic submodule over the interposer, and a module mold compound over the interposer and encapsulating sides of the shielded electronic submodule. Herein, the shielded electronic submodule includes an electronic submodule and a submodule side shielding structure, which covers sides of the electronic submodule to provide the sides of the shielded electronic submodule. A top surface of the electronic module is a combination of a top surface of the module mold compound and a top surface of the shielded electronic submodule, which is not covered by the module mold compound. The module shielding structure directly and continuously covers the top surface and sides of the electronic module, such that the submodule side shielding structure is electrically connected to the module shielding structure to individually shield the electronic submodule.
    Type: Application
    Filed: January 23, 2023
    Publication date: August 3, 2023
    Inventors: Thomas Scott Morris, Howard Terry Glascock, Charles E. Carpenter, Mudar AlJoumayly, Peter Cotterill
  • Patent number: 11387190
    Abstract: The present disclosure relates to a shielded electronic module, which includes a module substrate, an electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a second mold compound over a bottom surface of the module substrate, and a shielding structure. The second mold compound includes a recess extending inwardly from a bottom periphery of the second mold compound. The shielding structure completely covers a top surface of the module and extends over the side surface of the module until reaching the recess. Herein, the shielding structure is electrically grounded.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: July 12, 2022
    Assignee: QORVO US, INC.
    Inventors: Thomas Scott Morris, Stephen Craig Parker, Jerry Holt, John Davisson, Rommel Quintero Nevarez
  • Publication number: 20220052667
    Abstract: The disclosure is directed to an electronic device with a solder interconnect and multiple material encapsulant. The electronic device includes a die last assembly with the die assembled to an electronic packaging substrate by a solder interconnect. At least a portion of a first dielectric material and the die are milled or ground, with a second dielectric material applied over an exposed portion of the die. A shield is then positioned over and electrically insulated from the die. Accordingly, such a configuration reduces a thickness or height of an electronic device with shielding and a die last assembly.
    Type: Application
    Filed: June 17, 2021
    Publication date: February 17, 2022
    Inventors: Charles E. Carpenter, Howard Terry Glascock, Paul Stokes, Thomas Scott Morris
  • Patent number: 11219144
    Abstract: Electromagnetic shields for sub-modules of electronic modules are disclosed. Electronic modules may include multiple sub-modules arranged on a substrate with an electromagnetic shield arranged to conformally cover the sub-modules as well as portions of the substrate that are uncovered by the sub-modules. Electromagnetic shields are disclosed that are configured to extend between sub-modules to form one or more divider walls. The one or more divider walls may be configured to extend below mounting surfaces of electronic components in the sub-modules to provide improved reduction of electromagnetic interference (EMI) or crosstalk between various sub-modules. Electromagnetic shields are also disclosed that form perimeter sidewalls that extend below mounting surfaces of electronic components of sub-modules to provide improved reduction of EMI from other modules or other external sources.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: January 4, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Kelly M. Lear, Thomas Scott Morris, Jeffrey Miller, Jeffrey Dekosky
  • Patent number: 11127689
    Abstract: The present disclosure relates to segmented shielding using wirebonds. In an exemplary aspect, a shield is formed from a series of wires (e.g., wirebonds) to create a wall and/or shielded compartment in an integrated circuit (IC) module. The wires can be located in any area within the IC module. The IC module may be overmolded with an insulating mold compound, and a top surface of the insulating mold can be ground or otherwise removed to expose ends of the wires to a shield layer which surrounds the insulating mold. Some examples may further laser ablate or otherwise form cavities around the ends of the wires to create stronger bonding between the wires of the shield and the shield layer.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 21, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, Brian H. Calhoun, W. Kent Braxton, Domingo Farias, Joseph Edward Geniac, Kyle Sullivan, Donald Joseph Leahy
  • Patent number: 11058038
    Abstract: Electromagnetic shields for sub-modules of electronic modules are disclosed. Electronic modules may include multiple sub-modules arranged on a substrate with an electromagnetic shield arranged to conformally cover the sub-modules as well as portions of the substrate that are uncovered by the sub-modules. Electromagnetic shields are disclosed that are configured to extend between sub-modules to form one or more divider walls. The one or more divider walls may be configured to extend below mounting surfaces of electronic components in the sub-modules to provide improved reduction of electromagnetic interference (EMI) or crosstalk between various sub-modules. Electromagnetic shields are also disclosed that form perimeter sidewalls that extend below mounting surfaces of electronic components of sub-modules to provide improved reduction of EMI from other modules or other external sources.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: July 6, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Kelly M. Lear, Thomas Scott Morris, Jeffrey Miller, Jeffrey Dekosky
  • Patent number: 11024541
    Abstract: A process for molding a back side wafer singulation guide is disclosed. Structures for heat mitigation include an overmold formed over a contact surface of a device layer of a wafer, covering bump structures. The overmold and bump structures are thinned and planarized, and the overmold provides an underfill to increase interconnect reliability of a semiconductor die in a flip chip bonded package. However, visibility of singulation guides on the contact surface is obstructed. A channel is formed extending through the device layer and into the handle layer, and is filled with the overmold. The handle layer is replaced with a thermally-conductive molding layer formed on the back side for dissipating heat generated by semiconductor devices. The thermally-conductive handle is thinned until the overmold in the channel beneath the device layer is exposed. The exposed overmold provides a visible back side singulation guide for singulating the wafer.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 1, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Neftali Salazar, Rommel Quintero, Thomas Scott Morris
  • Publication number: 20210144853
    Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 13, 2021
    Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
  • Patent number: 10905007
    Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 26, 2021
    Assignee: Qorvo US, Inc.
    Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
  • Publication number: 20210020583
    Abstract: The present disclosure relates to a shielded electronic module, which includes a module substrate, an electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a second mold compound over a bottom surface of the module substrate, and a shielding structure. The second mold compound includes a recess extending inwardly from a bottom periphery of the second mold compound. The shielding structure completely covers a top surface of the module and extends over the side surface of the module until reaching the recess. Herein, the shielding structure is electrically grounded.
    Type: Application
    Filed: October 7, 2020
    Publication date: January 21, 2021
    Inventors: Thomas Scott Morris, Stephen Craig Parker, Jerry Holt, John Davisson, Rommel Quintero Nevarez
  • Publication number: 20210007224
    Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.
    Type: Application
    Filed: January 8, 2020
    Publication date: January 7, 2021
    Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
  • Patent number: 10888040
    Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: January 5, 2021
    Assignee: Qorvo US, Inc.
    Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
  • Patent number: 10856456
    Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: December 1, 2020
    Assignee: Qorvo US, Inc.
    Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
  • Patent number: 10811364
    Abstract: The present disclosure relates to a shielded electronic module, which includes a module substrate, an electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a second mold compound over a bottom surface of the module substrate, and a shielding structure. The second mold compound includes a recess extending inwardly from a bottom periphery of the second mold compound. The shielding structure completely covers a top surface of the module and extends over the side surface of the module until reaching the recess. Herein, the shielding structure is electrically grounded.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: October 20, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, Stephen Craig Parker, Jerry Holt, John Davisson, Rommel Quintero Nevarez
  • Publication number: 20200305314
    Abstract: Electromagnetic shields for sub-modules of electronic modules are disclosed. Electronic modules may include multiple sub-modules arranged on a substrate with an electromagnetic shield arranged to conformally cover the sub-modules as well as portions of the substrate that are uncovered by the sub-modules. Electromagnetic shields are disclosed that are configured to extend between sub-modules to form one or more divider walls. The one or more divider walls may be configured to extend below mounting surfaces of electronic components in the sub-modules to provide improved reduction of electromagnetic interference (EMI) or crosstalk between various sub-modules. Electromagnetic shields are also disclosed that form perimeter sidewalls that extend below mounting surfaces of electronic components of sub-modules to provide improved reduction of EMI from other modules or other external sources.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Kelly M. Lear, Thomas Scott Morris, Jeffrey Miller, Jeffrey Dekosky
  • Publication number: 20200303318
    Abstract: The present disclosure relates to a shielded electronic module, which includes a module substrate, an electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a second mold compound over a bottom surface of the module substrate, and a shielding structure. The second mold compound includes a recess extending inwardly from a bottom periphery of the second mold compound. The shielding structure completely covers a top surface of the module and extends over the side surface of the module until reaching the recess. Herein, the shielding structure is electrically grounded.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 24, 2020
    Inventors: Thomas Scott Morris, Stephen Craig Parker, Jerry Holt, John Davisson, Rommel Quintero Nevarez
  • Patent number: 10777524
    Abstract: A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 15, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, Michael Meeder
  • Publication number: 20200111708
    Abstract: A process for molding a back side wafer singulation guide is disclosed. Structures for heat mitigation include an overmold formed over a contact surface of a device layer of a wafer, covering bump structures. The overmold and bump structures are thinned and planarized, and the overmold provides an underfill to increase interconnect reliability of a semiconductor die in a flip chip bonded package. However, visibility of singulation guides on the contact surface is obstructed. A channel is formed extending through the device layer and into the handle layer, and is filled with the overmold. The handle layer is replaced with a thermally-conductive molding layer formed on the back side for dissipating heat generated by semiconductor devices. The thermally-conductive handle is thinned until the overmold in the channel beneath the device layer is exposed. The exposed overmold provides a visible back side singulation guide for singulating the wafer.
    Type: Application
    Filed: June 24, 2019
    Publication date: April 9, 2020
    Inventors: Neftali Salazar, Rommel Quintero, Thomas Scott Morris