Patents by Inventor Thomas Scott Morris
Thomas Scott Morris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230402333Abstract: A system in package (SiP) with an air cavity is disclosed. In one aspect, a technique to bond a lid over the air cavity that reduces the risk of cavity integrity failure is provided. More specifically, an epoxy seal is created on four walls of a lid enclosing the cavity. A further sputtered metal layer is added over the epoxy seal to provide additional structural rigidity, electromagnetic emission suppression and to assist in preventing leaks through the epoxy seal.Type: ApplicationFiled: May 16, 2023Publication date: December 14, 2023Inventors: MD Hasnine, Christine Blair, Thomas Scott Morris, Neftali Salazar
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Patent number: 11765826Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.Type: GrantFiled: January 25, 2021Date of Patent: September 19, 2023Assignee: Qorvo US, Inc.Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
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Publication number: 20230247814Abstract: The disclosure relates to a shielded electronic module which includes a module shielding structure and an electronic module with an interposer, a shielded electronic submodule over the interposer, and a module mold compound over the interposer and encapsulating sides of the shielded electronic submodule. Herein, the shielded electronic submodule includes an electronic submodule and a submodule side shielding structure, which covers sides of the electronic submodule to provide the sides of the shielded electronic submodule. A top surface of the electronic module is a combination of a top surface of the module mold compound and a top surface of the shielded electronic submodule, which is not covered by the module mold compound. The module shielding structure directly and continuously covers the top surface and sides of the electronic module, such that the submodule side shielding structure is electrically connected to the module shielding structure to individually shield the electronic submodule.Type: ApplicationFiled: January 23, 2023Publication date: August 3, 2023Inventors: Thomas Scott Morris, Howard Terry Glascock, Charles E. Carpenter, Mudar AlJoumayly, Peter Cotterill
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Patent number: 11387190Abstract: The present disclosure relates to a shielded electronic module, which includes a module substrate, an electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a second mold compound over a bottom surface of the module substrate, and a shielding structure. The second mold compound includes a recess extending inwardly from a bottom periphery of the second mold compound. The shielding structure completely covers a top surface of the module and extends over the side surface of the module until reaching the recess. Herein, the shielding structure is electrically grounded.Type: GrantFiled: October 7, 2020Date of Patent: July 12, 2022Assignee: QORVO US, INC.Inventors: Thomas Scott Morris, Stephen Craig Parker, Jerry Holt, John Davisson, Rommel Quintero Nevarez
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Publication number: 20220052667Abstract: The disclosure is directed to an electronic device with a solder interconnect and multiple material encapsulant. The electronic device includes a die last assembly with the die assembled to an electronic packaging substrate by a solder interconnect. At least a portion of a first dielectric material and the die are milled or ground, with a second dielectric material applied over an exposed portion of the die. A shield is then positioned over and electrically insulated from the die. Accordingly, such a configuration reduces a thickness or height of an electronic device with shielding and a die last assembly.Type: ApplicationFiled: June 17, 2021Publication date: February 17, 2022Inventors: Charles E. Carpenter, Howard Terry Glascock, Paul Stokes, Thomas Scott Morris
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Patent number: 11219144Abstract: Electromagnetic shields for sub-modules of electronic modules are disclosed. Electronic modules may include multiple sub-modules arranged on a substrate with an electromagnetic shield arranged to conformally cover the sub-modules as well as portions of the substrate that are uncovered by the sub-modules. Electromagnetic shields are disclosed that are configured to extend between sub-modules to form one or more divider walls. The one or more divider walls may be configured to extend below mounting surfaces of electronic components in the sub-modules to provide improved reduction of electromagnetic interference (EMI) or crosstalk between various sub-modules. Electromagnetic shields are also disclosed that form perimeter sidewalls that extend below mounting surfaces of electronic components of sub-modules to provide improved reduction of EMI from other modules or other external sources.Type: GrantFiled: April 22, 2019Date of Patent: January 4, 2022Assignee: Qorvo US, Inc.Inventors: Kelly M. Lear, Thomas Scott Morris, Jeffrey Miller, Jeffrey Dekosky
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Patent number: 11127689Abstract: The present disclosure relates to segmented shielding using wirebonds. In an exemplary aspect, a shield is formed from a series of wires (e.g., wirebonds) to create a wall and/or shielded compartment in an integrated circuit (IC) module. The wires can be located in any area within the IC module. The IC module may be overmolded with an insulating mold compound, and a top surface of the insulating mold can be ground or otherwise removed to expose ends of the wires to a shield layer which surrounds the insulating mold. Some examples may further laser ablate or otherwise form cavities around the ends of the wires to create stronger bonding between the wires of the shield and the shield layer.Type: GrantFiled: April 2, 2019Date of Patent: September 21, 2021Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, Brian H. Calhoun, W. Kent Braxton, Domingo Farias, Joseph Edward Geniac, Kyle Sullivan, Donald Joseph Leahy
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Patent number: 11058038Abstract: Electromagnetic shields for sub-modules of electronic modules are disclosed. Electronic modules may include multiple sub-modules arranged on a substrate with an electromagnetic shield arranged to conformally cover the sub-modules as well as portions of the substrate that are uncovered by the sub-modules. Electromagnetic shields are disclosed that are configured to extend between sub-modules to form one or more divider walls. The one or more divider walls may be configured to extend below mounting surfaces of electronic components in the sub-modules to provide improved reduction of electromagnetic interference (EMI) or crosstalk between various sub-modules. Electromagnetic shields are also disclosed that form perimeter sidewalls that extend below mounting surfaces of electronic components of sub-modules to provide improved reduction of EMI from other modules or other external sources.Type: GrantFiled: June 5, 2020Date of Patent: July 6, 2021Assignee: Qorvo US, Inc.Inventors: Kelly M. Lear, Thomas Scott Morris, Jeffrey Miller, Jeffrey Dekosky
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Patent number: 11024541Abstract: A process for molding a back side wafer singulation guide is disclosed. Structures for heat mitigation include an overmold formed over a contact surface of a device layer of a wafer, covering bump structures. The overmold and bump structures are thinned and planarized, and the overmold provides an underfill to increase interconnect reliability of a semiconductor die in a flip chip bonded package. However, visibility of singulation guides on the contact surface is obstructed. A channel is formed extending through the device layer and into the handle layer, and is filled with the overmold. The handle layer is replaced with a thermally-conductive molding layer formed on the back side for dissipating heat generated by semiconductor devices. The thermally-conductive handle is thinned until the overmold in the channel beneath the device layer is exposed. The exposed overmold provides a visible back side singulation guide for singulating the wafer.Type: GrantFiled: June 24, 2019Date of Patent: June 1, 2021Assignee: Qorvo US, Inc.Inventors: Neftali Salazar, Rommel Quintero, Thomas Scott Morris
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Publication number: 20210144853Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.Type: ApplicationFiled: January 25, 2021Publication date: May 13, 2021Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
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Patent number: 10905007Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.Type: GrantFiled: January 8, 2020Date of Patent: January 26, 2021Assignee: Qorvo US, Inc.Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
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Publication number: 20210020583Abstract: The present disclosure relates to a shielded electronic module, which includes a module substrate, an electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a second mold compound over a bottom surface of the module substrate, and a shielding structure. The second mold compound includes a recess extending inwardly from a bottom periphery of the second mold compound. The shielding structure completely covers a top surface of the module and extends over the side surface of the module until reaching the recess. Herein, the shielding structure is electrically grounded.Type: ApplicationFiled: October 7, 2020Publication date: January 21, 2021Inventors: Thomas Scott Morris, Stephen Craig Parker, Jerry Holt, John Davisson, Rommel Quintero Nevarez
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Publication number: 20210007224Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.Type: ApplicationFiled: January 8, 2020Publication date: January 7, 2021Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
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Patent number: 10888040Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.Type: GrantFiled: August 28, 2018Date of Patent: January 5, 2021Assignee: Qorvo US, Inc.Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
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Patent number: 10856456Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.Type: GrantFiled: August 28, 2018Date of Patent: December 1, 2020Assignee: Qorvo US, Inc.Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
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Patent number: 10811364Abstract: The present disclosure relates to a shielded electronic module, which includes a module substrate, an electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a second mold compound over a bottom surface of the module substrate, and a shielding structure. The second mold compound includes a recess extending inwardly from a bottom periphery of the second mold compound. The shielding structure completely covers a top surface of the module and extends over the side surface of the module until reaching the recess. Herein, the shielding structure is electrically grounded.Type: GrantFiled: March 18, 2019Date of Patent: October 20, 2020Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, Stephen Craig Parker, Jerry Holt, John Davisson, Rommel Quintero Nevarez
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Publication number: 20200305314Abstract: Electromagnetic shields for sub-modules of electronic modules are disclosed. Electronic modules may include multiple sub-modules arranged on a substrate with an electromagnetic shield arranged to conformally cover the sub-modules as well as portions of the substrate that are uncovered by the sub-modules. Electromagnetic shields are disclosed that are configured to extend between sub-modules to form one or more divider walls. The one or more divider walls may be configured to extend below mounting surfaces of electronic components in the sub-modules to provide improved reduction of electromagnetic interference (EMI) or crosstalk between various sub-modules. Electromagnetic shields are also disclosed that form perimeter sidewalls that extend below mounting surfaces of electronic components of sub-modules to provide improved reduction of EMI from other modules or other external sources.Type: ApplicationFiled: June 5, 2020Publication date: September 24, 2020Inventors: Kelly M. Lear, Thomas Scott Morris, Jeffrey Miller, Jeffrey Dekosky
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Publication number: 20200303318Abstract: The present disclosure relates to a shielded electronic module, which includes a module substrate, an electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a second mold compound over a bottom surface of the module substrate, and a shielding structure. The second mold compound includes a recess extending inwardly from a bottom periphery of the second mold compound. The shielding structure completely covers a top surface of the module and extends over the side surface of the module until reaching the recess. Herein, the shielding structure is electrically grounded.Type: ApplicationFiled: March 18, 2019Publication date: September 24, 2020Inventors: Thomas Scott Morris, Stephen Craig Parker, Jerry Holt, John Davisson, Rommel Quintero Nevarez
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Patent number: 10777524Abstract: A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.Type: GrantFiled: August 27, 2018Date of Patent: September 15, 2020Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, Michael Meeder
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Publication number: 20200111708Abstract: A process for molding a back side wafer singulation guide is disclosed. Structures for heat mitigation include an overmold formed over a contact surface of a device layer of a wafer, covering bump structures. The overmold and bump structures are thinned and planarized, and the overmold provides an underfill to increase interconnect reliability of a semiconductor die in a flip chip bonded package. However, visibility of singulation guides on the contact surface is obstructed. A channel is formed extending through the device layer and into the handle layer, and is filled with the overmold. The handle layer is replaced with a thermally-conductive molding layer formed on the back side for dissipating heat generated by semiconductor devices. The thermally-conductive handle is thinned until the overmold in the channel beneath the device layer is exposed. The exposed overmold provides a visible back side singulation guide for singulating the wafer.Type: ApplicationFiled: June 24, 2019Publication date: April 9, 2020Inventors: Neftali Salazar, Rommel Quintero, Thomas Scott Morris