Patents by Inventor Thomas Scott Morris
Thomas Scott Morris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9859132Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: GrantFiled: June 3, 2016Date of Patent: January 2, 2018Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Patent number: 9661739Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.Type: GrantFiled: January 13, 2015Date of Patent: May 23, 2017Assignee: Qorvo US, Inc.Inventors: Donald Joseph Leahy, Brian D. Sawyer, Stephen Parker, Thomas Scott Morris
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Patent number: 9646857Abstract: The present disclosure relates to a packaging process using a low pressure encapsulant. According to an exemplary process, an assembly including a substrate, a surface mounted device (SMD) mounted on the substrate, and a space between the SMD and the substrate is provided. The SMD has a sealed cavity biased towards the substrate. A sheet mold compound is laid over the SMD and the assembly is heated such that the sheet mold compound transitions to a liquid phase to form a molten mold compound. Next, the assembly is subjected to a vacuum that creates a negative atmosphere allowing the molten mold compound to flow towards the top surface of the substrate and about the SMD. The molten mold compound is then pressed towards the substrate at a low pressure (<=2 Mpa) such that the space between the SMD and the substrate is substantially filled and the SMD is substantially encapsulated.Type: GrantFiled: August 15, 2016Date of Patent: May 9, 2017Assignee: Qorvo US, Inc.Inventors: Howard Terry Glascock, Frank Juskey, Thomas Scott Morris, Charles E. Carpenter, Robert Hartmann
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Patent number: 9613831Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: GrantFiled: December 4, 2015Date of Patent: April 4, 2017Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Patent number: 9576822Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: GrantFiled: December 4, 2015Date of Patent: February 21, 2017Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Publication number: 20170047232Abstract: The present disclosure relates to a packaging process using a low pressure encapsulant. According to an exemplary process, an assembly including a substrate, a surface mounted device (SMD) mounted on the substrate, and a space between the SMD and the substrate is provided. The SMD has a sealed cavity biased towards the substrate. A sheet mold compound is laid over the SMD and the assembly is heated such that the sheet mold compound transitions to a liquid phase to form a molten mold compound. Next, the assembly is subjected to a vacuum that creates a negative atmosphere allowing the molten mold compound to flow towards the top surface of the substrate and about the SMD. The molten mold compound is then pressed towards the substrate at a low pressure (<=2 Mpa) such that the space between the SMD and the substrate is substantially filled and the SMD is substantially encapsulated.Type: ApplicationFiled: August 15, 2016Publication date: February 16, 2017Inventors: Howard Terry Glascock, Frank Juskey, Thomas Scott Morris, Charles E. Carpenter, Robert Hartmann
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Publication number: 20170040273Abstract: The present disclosure relates to a semiconductor package having a substrate structure with selective surface finishes, and a process for making the same. The disclosed semiconductor package includes a substrate body, a first metal structure having a first finish area and a second finish area, a second metal structure having a third finish area, a surface finish, and a tuning wire. The first metal structure and the second metal structure are formed over the substrate body. The surface finish is provided over the first finish area of the first metal structure and at least a portion of the third finish area of the second metal structure. The surface finish is not provided over the second finish area of the first metal structure. The tuning wire is coupled between the first finish area and at least one portion of the third finish area.Type: ApplicationFiled: August 1, 2016Publication date: February 9, 2017Inventors: Thomas Scott Morris, Robert Hartmann
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Publication number: 20170040276Abstract: The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish.Type: ApplicationFiled: August 1, 2016Publication date: February 9, 2017Inventors: Thomas Scott Morris, Robert Hartmann
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Publication number: 20170018520Abstract: A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.Type: ApplicationFiled: September 28, 2016Publication date: January 19, 2017Inventors: Thomas Scott Morris, Michael Meeder
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Publication number: 20160343592Abstract: A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound residing on the top surface. A first mold compound is disposed on the top surface of the carrier. A first thinned flip chip die resides over a first portion of the first mold compound with interconnects extending through the first portion to the top surface wherein the first portion of the mold compound fills a region between the first flip chip die and the top surface. A second mold compound resides over the substrate and provides a first recess over the first flip chip die wherein the first recess extends to a first die surface of the first flip chip die. A third mold compound resides in the first recess and covers an exposed surface of the flip chip die.Type: ApplicationFiled: August 5, 2016Publication date: November 24, 2016Inventors: Julio C. Costa, Thomas Scott Morris, Jonathan Hale Hammond, David Jandzinski, Stephen Parker, Jon Chadwick
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Publication number: 20160284568Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: ApplicationFiled: December 4, 2015Publication date: September 29, 2016Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Publication number: 20160284570Abstract: The present disclosure relates to a semiconductor package having encapsulated dies with enhanced thermal performance. The semiconductor package includes a carrier, an etched flip chip die attached to a top surface of the carrier, a first mold compound, and a second mold compound. The etched flip chip die includes a device layer and essentially does not include a substrate. The first mold compound resides on the top surface of the carrier, surrounds the etched flip chip die, and extends beyond a top surface of the etched flip chip die to form a cavity, to which the top surface of the etched flip chip die is exposed. The second mold compound fills the cavity and is in contact with the top surface of the etched flip chip die. The second mold compound having a high thermal conductivity improves thermal performance of the etched flip chip die.Type: ApplicationFiled: June 3, 2016Publication date: September 29, 2016Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Patent number: 9420704Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.Type: GrantFiled: July 31, 2014Date of Patent: August 16, 2016Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, Ulrik Riis Madsen, Donald Joseph Leahy
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Publication number: 20150296631Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.Type: ApplicationFiled: June 25, 2015Publication date: October 15, 2015Inventors: Thomas Scott Morris, Ulrik Riis Madsen, Donald Joseph Leahy
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Patent number: 9137934Abstract: Embodiments include devices and methods for manufacturing a module having a first shielded compartment and a second shielded compartment, wherein the first shielded compartment is electrically isolated from the second shielded compartment. Electrical conductivity is controlled in a manner in which current flow between shielded circuits is directed to reduce or eliminate energy from being coupled between one or more shielded compartments on the same module. Each module may have a plurality of individual shielded compartments, where each compartment has a dedicated ground plane. The shields for each compartment may be tied to the dedicated ground plane of the compartment. Because the dedicated ground planes are not tied together, each of the shielded compartments on the modules remains isolated from all the other shielded compartments on the modules. In some embodiments having a plurality of shielded compartments, there is at least one isolated shielded compartment depending upon the design needs of the module.Type: GrantFiled: July 25, 2011Date of Patent: September 15, 2015Assignee: RF Micro Devices, Inc.Inventors: Thomas Scott Morris, Ulrik Riis Madsen, Brian D. Sawyer, Milind Shah, John Robert Siomkos, Mark Alan Crandall, Dan Carey
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Publication number: 20150124421Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.Type: ApplicationFiled: January 13, 2015Publication date: May 7, 2015Inventors: Donald Joseph Leahy, Brian D. Sawyer, Stephen Parker, Thomas Scott Morris
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Patent number: 8959762Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.Type: GrantFiled: February 25, 2011Date of Patent: February 24, 2015Assignee: RF Micro Devices, Inc.Inventors: Donald Joseph Leahy, Brian D. Sawyer, Stephen Parker, Thomas Scott Morris
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Publication number: 20140340859Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: Thomas Scott Morris, Ulrik Riis Madsen, Donald Joseph Leahy
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Patent number: 8835226Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.Type: GrantFiled: February 25, 2011Date of Patent: September 16, 2014Assignee: RF Micro Devices, Inc.Inventors: Thomas Scott Morris, Ulrik Riis Madsen, Donald Joseph Leahy
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Publication number: 20140146489Abstract: An electronic substrate includes a non-conductive body and one or more conductive features coupled to the non-conductive body. Each of the conductive features includes a base layer. To preserve the performance and conductivity of the one or more conductive features, each of the conductive features includes a protective layer formed over the base layer. The protective layer may include a first layer of silver formed over the base layer and a second layer of palladium formed over the first layer. By depositing the protective layer over the base layer of each of the conductive features, oxidation and exposure of the conductive features is prevented, or at least substantially reduced, since the first layer and the second layer provide a migration barrier for the metal in the base layer. However, the performance and conductivity of the conductive features are maintained due to the low resistivity of silver and palladium.Type: ApplicationFiled: May 10, 2013Publication date: May 29, 2014Inventors: John August Orlowski, Donald Joseph Leahy, Thomas Scott Morris, David C. Dening, David Jandzinski