Patents by Inventor Thorsten Scharf

Thorsten Scharf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220157774
    Abstract: A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.
    Type: Application
    Filed: October 15, 2021
    Publication date: May 19, 2022
    Applicant: Infineon Technologies AG
    Inventors: Thorsten MEYER, Martin GRUBER, Thorsten SCHARF
  • Patent number: 11309277
    Abstract: Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: April 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Thorsten Scharf, Ralf Wombacher
  • Publication number: 20220108974
    Abstract: A method of forming a chip package is provided. The method includes providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier. The layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip. The layer forms a redistribution layer.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 7, 2022
    Inventors: Thorsten Scharf, Alexander Heinrich, Steffen Jordan
  • Publication number: 20220068773
    Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 3, 2022
    Inventors: Thorsten Scharf, Chan Lam Cha, Wolfgang Hetzel, Swee Kah Lee, Stefan Macheiner
  • Patent number: 11264356
    Abstract: A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: March 1, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Thomas Behrens, Andreas Grassmann, Martin Gruber, Thorsten Scharf
  • Publication number: 20220045031
    Abstract: A method for fabricating a semiconductor device includes providing a semiconductor die, arranging an electrical connector over the semiconductor die, the electrical connector including a conductive core, an absorbing feature arranged on a first side of the conductive core, and a solder layer arranged on a second side of the conductive core, opposite the first side and facing the semiconductor die, and soldering the electrical connector onto the semiconductor die by heating the solder layer with a laser, wherein the laser irradiates the absorbing feature and absorbed energy is transferred from the absorbing feature through the conductive core to the solder layer.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 10, 2022
    Inventors: Richard Knipper, Alexander Heinrich, Thorsten Scharf, Stefan Schwab
  • Publication number: 20220005755
    Abstract: The semiconductor device package comprises a die carrier, at least one semiconductor die disposed on the carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier, an encapsulant disposed above the semiconductor die, an electrical connector electrically connected with the contact pad, a drilling screw screwed through the encapsulant and connected with the electrical connector.
    Type: Application
    Filed: June 28, 2021
    Publication date: January 6, 2022
    Inventors: Thorsten Scharf, Thomas Bemmerl, Martin Gruber, Thorsten Meyer, Frank Singer
  • Publication number: 20210217633
    Abstract: A semiconductor device includes: a first semiconductor die having opposing first and second main surfaces and an edge between the first and second main surfaces; a molding compound covering the edge and a peripheral part of the first main surface of the first semiconductor die, the molding compound including a resin and filler particles embedded within the resin; and a first opening in the molding compound which exposes a first part of the first main surface of the first semiconductor die from the molding compound, the first part being positioned inward from the peripheral part, wherein the first opening in the molding compound has a sidewall, wherein predominantly all of the filler particles disposed along the sidewall of the first opening are fully embedded within the resin and not exposed at all along the sidewall. A semiconductor structure including a semiconductor wafer or panel is also described.
    Type: Application
    Filed: March 30, 2021
    Publication date: July 15, 2021
    Inventors: Richard Knipper, Thorsten Scharf
  • Publication number: 20210166998
    Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.
    Type: Application
    Filed: February 16, 2021
    Publication date: June 3, 2021
    Inventors: Thorsten Scharf, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Bun Kian Tay
  • Publication number: 20210151401
    Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.
    Type: Application
    Filed: January 26, 2021
    Publication date: May 20, 2021
    Applicant: Infineon Technologies AG
    Inventors: Petteri Palm, Thorsten Scharf
  • Patent number: 11004700
    Abstract: A method includes: providing a semiconductor die having a first main surface, a second main surface opposite the first main surface, and an edge between the first main surface and the second main surface; applying a temporary spacer to a first part of the first main surface of the semiconductor die, the first part being positioned inward from a peripheral part of the first main surface; after applying the temporary spacer, embedding the semiconductor die at least partly in an embedding material, the embedding material covering the edge and the peripheral part of the first main surface of the semiconductor die and contacting a sidewall of the temporary spacer; and after the embedding, removing the temporary spacer from the first main surface of the semiconductor die to expose the first part of the first main surface of the semiconductor die. A semiconductor device produced by the method is also provided.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: May 11, 2021
    Assignee: Infineon Technologies AG
    Inventors: Richard Knipper, Thorsten Scharf
  • Publication number: 20210111108
    Abstract: A package is disclosed. In one example, the package comprises a substrate having at least one first recess on a front side and at least one second recess on a back side, wherein the substrate is separated into a plurality of separate substrate sections by the at least one first recess and the at least one second recess, an electronic component mounted on the front side of the substrate, and a single encapsulant filling at least part of the at least one first recess and at least part of the at least one second recess. The encapsulant fully circumferentially surrounds sidewalls of at least one of the substrate sections.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 15, 2021
    Applicant: Infineon Technologies AG
    Inventors: Frank Singer, Martin Gruber, Thorsten Meyer, Thorsten Scharf, Peter Strobel, Stefan Woetzel
  • Patent number: 10971457
    Abstract: A semiconductor device is disclosed. In one example, the semiconductor device comprises a first semiconductor die comprising a first surface, a second surface opposite to the first surface, and a contact pad disposed on the first surface, a further contact pad spaced apart from the semiconductor die, a clip comprising a first layer of a first metallic material and a second layer of a second metallic material different from the first metallic material, wherein the first layer of the clip is connected with the contact pad, and the second layer of the clip is connected with the further contact pad.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Bemmerl, Martin Gruber, Thorsten Scharf
  • Patent number: 10964628
    Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 30, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Scharf, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Bun Kian Tay
  • Publication number: 20210057234
    Abstract: A method includes: providing a semiconductor die having a first main surface, a second main surface opposite the first main surface, and an edge between the first main surface and the second main surface; applying a temporary spacer to a first part of the first main surface of the semiconductor die, the first part being positioned inward from a peripheral part of the first main surface; after applying the temporary spacer, embedding the semiconductor die at least partly in an embedding material, the embedding material covering the edge and the peripheral part of the first main surface of the semiconductor die and contacting a sidewall of the temporary spacer; and after the embedding, removing the temporary spacer from the first main surface of the semiconductor die to expose the first part of the first main surface of the semiconductor die. A semiconductor device produced by the method is also provided.
    Type: Application
    Filed: August 21, 2019
    Publication date: February 25, 2021
    Inventors: Richard Knipper, Thorsten Scharf
  • Publication number: 20210035879
    Abstract: A package and method of manufacturing a package is disclosed. In one example, the method comprises mounting at least one electronic component on a carrier, attaching a laminate body to the mounted at least one electronic component, and filling at least part of spaces between the laminate body and the carrier with mounted at least one electronic component with an encapsulant.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 4, 2021
    Applicant: Infineon Technologies AG
    Inventors: Angela Kessler, Thorsten Scharf
  • Patent number: 10903180
    Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Thorsten Scharf
  • Publication number: 20210005557
    Abstract: A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 7, 2021
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Meyer, Thomas Behrens, Martin Gruber, Thorsten Scharf, Peter Strobel
  • Patent number: 10886186
    Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: January 5, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Scharf, Ralf Otremba, Thomas Bemmerl, Irmgard Escher-Poeppel, Martin Gruber, Michael Juerss, Thorsten Meyer, Xaver Schloegel
  • Publication number: 20200365553
    Abstract: A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.
    Type: Application
    Filed: April 7, 2020
    Publication date: November 19, 2020
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Meyer, Thomas Behrens, Andreas Grassmann, Martin Gruber, Thorsten Scharf