Patents by Inventor Thorsten Scharf

Thorsten Scharf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118614
    Abstract: A molded package includes: a mold compound; a first power semiconductor die encapsulated by the mold compound; and a first temperature sense cavity formed in a surface of the mold compound. The molded package is devoid of temperature sense terminals. The first temperature sense cavity is dimensioned to receive a temperature sensor and/or a combined area of each sidewall and a bottom of the first temperature sense cavity is greater than an area of an opening in the surface of the mold compound that delineates the first temperature sense cavity. A corresponding power module and a power electronics assembly that includes the molded package or the power module are also described.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Inventors: Thorsten Scharf, Michael Fügl
  • Patent number: 12249561
    Abstract: A method of forming a semiconductor package includes providing a first metal substrate; and mounting a stacked arrangement on the first metal substrate, the stacked arrangement comprising a semiconductor die, wherein mounting the stacked arrangement includes: providing a first layer of attachment material between the first metal substrate and the stacked arrangement; and providing a second layer of attachment material within the stacked arrangement at an interface with the semiconductor die, wherein at least one of the first and second layers of attachment material is a compressible layer that includes one or more elastomeric elements embedded within a matrix of solder material.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: March 11, 2025
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Scharf, Frank Singer
  • Publication number: 20250079275
    Abstract: A package is disclosed. In one example, the package comprises a carrier, a first chip with an integrated transistor and comprising a first terminal attached on the carrier, a second terminal, and a third terminal, wherein the first terminal and the third terminal are formed on one main surface of the first chip and the second terminal is formed on an opposing other main surface of the first chip. A conductive structure is attached on the second terminal, an encapsulant is at least partially encapsulating the carrier, the first chip, and the conductive structure, and an insulating layer is arranged on a surface portion of the conductive structure or of the carrier. The surface portion is exposed beyond the encapsulant.
    Type: Application
    Filed: July 23, 2024
    Publication date: March 6, 2025
    Applicant: Infineon Technologies AG
    Inventors: Wolfgang SCHOLZ, Marcus BÖHM, Bernd Richard SCHMÖLZER, Andre Rainer STEGNER, Lisa Marie HOLZMANN, Thorsten SCHARF
  • Publication number: 20250062290
    Abstract: A power semiconductor package includes a plurality of first power semiconductor dies attached to a first metallization layer and a plurality of second power semiconductor dies attached to a second metallization layer. A first structured metal frame disposed above the first metallization layer is electrically connected to a load terminal of each first power semiconductor die. A second structured metal frame disposed above the second metallization layer is electrically connected to a load terminal of each second power semiconductor die and to the first metallization layer. A first lead is electrically connected to the second metallization layer. A second lead is electrically connected to the second metallization layer. A third lead interposed between the first and second leads is electrically connected to the first structured metal frame. A fourth lead is electrically connected to the second structured metal frame.
    Type: Application
    Filed: November 1, 2024
    Publication date: February 20, 2025
    Inventors: Ivan Nikitin, Thorsten Scharf, Marco Bãßler, Andreas Grassmann, Waldemar Jakobi
  • Patent number: 12218098
    Abstract: An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: February 4, 2025
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Thorsten Scharf, Ralf Wombacher
  • Patent number: 12211824
    Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.
    Type: Grant
    Filed: April 5, 2023
    Date of Patent: January 28, 2025
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Thorsten Scharf, Marco Bäßler, Andreas Grassmann, Waldemar Jakobi
  • Publication number: 20240395676
    Abstract: A package includes a single integral electrically conductive body, a first chip with an integrated transistor and including a first terminal, a second terminal, and a third terminal, wherein the second terminal and the third terminal are formed on one main surface of the first chip and the first terminal is formed on an opposing main surface of the first chip, and a second chip with an integrated transistor and comprising a fourth, fifth and sixth terminals, wherein the fourth terminal and the sixth terminal are formed on one main surface of the second chip and the fifth terminal is formed on another surface of the second chip, wherein the first chip and the second chip are connected to form a half bridge.
    Type: Application
    Filed: May 21, 2024
    Publication date: November 28, 2024
    Inventors: Marcus Böhm, Bernd Richard Schmölzer, Lisa Marie Holzmann, Thorsten Scharf
  • Patent number: 12154886
    Abstract: A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: November 26, 2024
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Martin Gruber, Thorsten Scharf
  • Publication number: 20240355767
    Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: Infineon Technologies AG
    Inventors: Petteri Palm, Thorsten Scharf
  • Publication number: 20240347369
    Abstract: A method is disclosed. In one example, the method comprises mounting an electronic component on an adhesive base structure on a temporary carrier, and dissolving at least part of the base structure by irradiating the base structure with electromagnetic radiation to thereby release the electronic component.
    Type: Application
    Filed: March 14, 2024
    Publication date: October 17, 2024
    Applicant: Infineon Technologies AG
    Inventors: Frank SINGER, Thorsten SCHARF, Evelyn NAPETSCHNIG
  • Publication number: 20240332142
    Abstract: A power semiconductor module includes an encapsulation encapsulating power semiconductor dies. The encapsulation includes lateral sides connecting first and second opposite sides. First and second power contacts are electrically coupled to the power semiconductor dies. An isolation part arranged between the power contacts electrically isolates the contacts from one another. The power contacts have a flat shape and are stacked such that their broadest surfaces at least partially overlap. A first portion of the power contacts is parallel to a first plane. A second portion is twisted and/or bent with respect to the first portion such that the second portion is parallel to a second plane arranged at a non-zero angle with respect to the first plane. At least a part of the first portion is encapsulated by the encapsulation. At least a part of the second portion is exposed from the encapsulation at one of the lateral sides.
    Type: Application
    Filed: March 19, 2024
    Publication date: October 3, 2024
    Inventors: Michael Fügl, Thorsten Scharf
  • Publication number: 20240332136
    Abstract: A power semiconductor device includes: at least one substrate; at least one power semiconductor die arranged over the at least one substrate; a first leadframe arranged over the at least one power semiconductor substrate and over the at least one power semiconductor die, the first leadframe being arranged at least partially in a first plane and including one or more connecting portions extending out of the first plane in a first direction; and a second leadframe at least partially arranged in a second plane above or below the first plane and including one or more attachment sites. The one or more connecting portions extend into the second plane at the one or more attachment sites. The one or more connecting portions are arranged at a non-zero distance from the second leadframe, the non-zero distance being bridged by weld seams at the one or more attachment sites.
    Type: Application
    Filed: March 19, 2024
    Publication date: October 3, 2024
    Inventors: Marco Bäßler, Michal Chajneta, Thorsten Scharf, Egbert Lamminger
  • Patent number: 12027490
    Abstract: A method for fabricating a semiconductor device includes providing a semiconductor die, arranging an electrical connector over the semiconductor die, the electrical connector including a conductive core, an absorbing feature arranged on a first side of the conductive core, and a solder layer arranged on a second side of the conductive core, opposite the first side and facing the semiconductor die, and soldering the electrical connector onto the semiconductor die by heating the solder layer with a laser, wherein the laser irradiates the absorbing feature and absorbed energy is transferred from the absorbing feature through the conductive core to the solder layer.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: July 2, 2024
    Assignee: Infineon Technologies AG
    Inventors: Richard Knipper, Alexander Heinrich, Thorsten Scharf, Stefan Schwab
  • Patent number: 12027481
    Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: July 2, 2024
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Thorsten Scharf
  • Publication number: 20240186225
    Abstract: A method of fabricating a semiconductor device package includes: providing a die carrier; disposing at least one semiconductor die on the die carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier; electrically connecting the semiconductor die or another electrical device with an electrical connector; applying an encapsulant above the semiconductor die, the die carrier, and the electrical connector; and screwing a metallic drilling screw through the encapsulant so that an end of the drilling screw contacts the electrical connector.
    Type: Application
    Filed: February 15, 2024
    Publication date: June 6, 2024
    Inventors: Thorsten Scharf, Thomas Bemmerl, Martin Gruber, Thorsten Meyer, Frank Singer
  • Publication number: 20240178109
    Abstract: A semiconductor package includes a semiconductor die thermally coupled to a planar metal pad, an encapsulant body that encapsulates the semiconductor die and includes a recess that extends from an outer upper side of the encapsulant body towards a rear side of the planar metal pad, and an insert arranged within the recess that is thermally coupled to the planar metal pad and extends to the outer upper side of the encapsulant body, wherein the insert that is arranged within the recess includes a curable polymer compound.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Stefan Schwab, Michael Juerss, Thorsten Scharf
  • Patent number: 11955415
    Abstract: The semiconductor device package comprises a die carrier, at least one semiconductor die disposed on the carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier, an encapsulant disposed above the semiconductor die, an electrical connector electrically connected with the contact pad, a drilling screw screwed through the encapsulant and connected with the electrical connector.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: April 9, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Thorsten Scharf, Thomas Bemmerl, Martin Gruber, Thorsten Meyer, Frank Singer
  • Publication number: 20240105678
    Abstract: A chip package is provided. The chip package includes an electrically conductive carrier structure, a first power chip on the carrier structure having a control contact pad and a second power chip on the carrier structure having a control contact pad. The first and second power chips are arranged with their respective control contact pad facing a redistribution layer. A logic chip is arranged with a logic contact pad facing a redistribution layer, wherein the redistribution layer connects the logic contact pad with the respective control pads of the power chips.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 28, 2024
    Applicant: Infineon Technologies AG
    Inventors: Thorsten MEYER, Angela KESSLER, Thorsten SCHARF
  • Patent number: 11915999
    Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: February 27, 2024
    Assignee: Infineon Technologies AG
    Inventors: Tomasz Naeve, Ralf Otremba, Thorsten Scharf, Markus Dinkel, Martin Gruber, Elvir Kahrimanovic
  • Patent number: 11908830
    Abstract: A method for fabricating a semiconductor device includes providing a semiconductor die, arranging an electrical connector over the semiconductor die, the electrical connector including a conductive core, an absorbing feature arranged on a first side of the conductive core, and a solder layer arranged on a second side of the conductive core, opposite the first side and facing the semiconductor die, and soldering the electrical connector onto the semiconductor die by heating the solder layer with a laser, wherein the laser irradiates the absorbing feature and absorbed energy is transferred from the absorbing feature through the conductive core to the solder layer.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: February 20, 2024
    Assignee: Infineon Technologies AG
    Inventors: Richard Knipper, Alexander Heinrich, Thorsten Scharf, Stefan Schwab