Abstract: A square baler. The square baler includes: at least one ram arranged movably between end positions in a pressing channel, and a cutting rotor, and a drive train which is designed to drive at least the ram and the cutting rotor together, a torque input connection through which torque may be supplied to the drive train, and a first power split, such as a bevel gear stage, which is connected to the torque input connection. The drive train includes at least one reduction gear associated with the ram. The reduction gear associated with the ram and the cutting rotor are connected in parallel to each other to the first power split. At least one side gear is connected between the first power split and the at least one reduction gear associated with the ram. And, at least one flywheel is connected between the at least one reduction gear associated with the ram and the at least one side gear.

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

Abstract: A gear assembly is disclosed for driving a ram arranged in a pressing channel of a square baler so as to be movable between end positions. The gear assembly comprises at least one side gear, which may be driven indirectly by a power take-off shaft of an agricultural production machine, and at least one reduction gear which is connected downstream from the at least one side gear and may be connected on the output side to a crankshaft on which the ram is mounted. The gear assembly further includes at least one flywheel that is connected between the at least one side gear and the at least one reduction gear, and at least one shiftable clutch device that is connected between the at least one flywheel and the at least one reduction gear.

Abstract: A method for producing a molded electronic devices includes providing a first metallic frame including a plurality of die pads and a plurality of first connectors that hold the die pads in place. A vertical power semiconductor die is attached to each die pad. One or more second metallic frames are vertically aligned with the first metallic frame. Each second metallic frame includes a plurality of first contact pads and a plurality of second connectors that hold the first contact pads in place. Each of the first contact pads is attached to a load terminal of one of the vertical power semiconductor dies without any direct physical or electrical connection between the first metallic frame and the second metallic frame. The vertical power semiconductor dies are encapsulated in a mold compound. The first connectors and the second connectors are severed to yield individual molded electronic devices.

Abstract: An electronic component includes a plurality of power semiconductor dies, a first terminal, a second terminal separate from the first terminal, and a shunt. The power semiconductor dies are attached to a substrate. The shunt has a first side attached to the first terminal, and a second side opposite the first side. The electronic component includes a first connection between a first contact pad of each of the power semiconductor dies and the second side of the shunt, and a second connection between the second terminal and the second side of the shunt. The shunt has a higher specific resistance than the first connection. A resistance of the shunt varies by less than 10 percent over a normal operating temperature range of the electronic component.

Abstract: A molded electronic component includes a power semiconductor die, a load terminal, a sense terminal separate from the load terminal, and a shunt. The power semiconductor die is at least partly embedded in a mold compound. The load terminal and the sense terminal are each partly embedded in the mold compound. A first side of the shunt is attached to the load terminal. The molded electronic component includes a first connection between a first contact pad of the power semiconductor die and a second side of the shunt opposite the first side, and a second connection between the sense terminal and the second side of the shunt. The shunt has a higher specific resistance than the first connection. A resistance of the shunt varies by less than 10 percent over a normal operating temperature range of the molded electronic component.

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

Abstract: A method of fabricating a semiconductor device package includes: providing a die carrier; disposing at least one semiconductor die on the die carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier; electrically connecting the semiconductor die or another electrical device with an electrical connector; applying an encapsulant above the semiconductor die, the die carrier, and the electrical connector; and screwing a metallic drilling screw through the encapsulant so that an end of the drilling screw contacts the electrical connector.

Abstract: An electronic component includes an enclosure, a power circuit, a positive supply terminal and a negative supply terminal, and a metallic body. The power circuit is disposed in the enclosure. The positive supply terminal and negative supply terminal are each exposed from the enclosure. The positive supply terminal and the negative supply terminal are separated from one another by a gap and extend adjacent to each other in a longitudinal direction. The positive supply terminal is electrically coupled to a first terminal of the power circuit and the negative supply terminal is electrically coupled to a second terminal of the power circuit. The metallic body is attached and electrically coupled to one of the positive supply terminal or the negative supply terminal. The metallic body extends along the positive supply terminal and the negative supply terminal in the longitudinal direction.

Abstract: A package and method of manufacturing a package is disclosed. In one example, the method comprises mounting at least one electronic component on a carrier, attaching a laminate body to the mounted at least one electronic component, and filling at least part of spaces between the laminate body and the carrier with mounted at least one electronic component with an encapsulant.

Abstract: A molded package includes: a mold compound; a first power semiconductor die encapsulated by the mold compound; and a first temperature sense cavity formed in a surface of the mold compound. The molded package is devoid of temperature sense terminals. The first temperature sense cavity is dimensioned to receive a temperature sensor and/or a combined area of each sidewall and a bottom of the first temperature sense cavity is greater than an area of an opening in the surface of the mold compound that delineates the first temperature sense cavity. A corresponding power module and a power electronics assembly that includes the molded package or the power module are also described.

Abstract: A method of forming a semiconductor package includes providing a first metal substrate; and mounting a stacked arrangement on the first metal substrate, the stacked arrangement comprising a semiconductor die, wherein mounting the stacked arrangement includes: providing a first layer of attachment material between the first metal substrate and the stacked arrangement; and providing a second layer of attachment material within the stacked arrangement at an interface with the semiconductor die, wherein at least one of the first and second layers of attachment material is a compressible layer that includes one or more elastomeric elements embedded within a matrix of solder material.

Abstract: A package is disclosed. In one example, the package comprises a carrier, a first chip with an integrated transistor and comprising a first terminal attached on the carrier, a second terminal, and a third terminal, wherein the first terminal and the third terminal are formed on one main surface of the first chip and the second terminal is formed on an opposing other main surface of the first chip. A conductive structure is attached on the second terminal, an encapsulant is at least partially encapsulating the carrier, the first chip, and the conductive structure, and an insulating layer is arranged on a surface portion of the conductive structure or of the carrier. The surface portion is exposed beyond the encapsulant.

Abstract: A power semiconductor package includes a plurality of first power semiconductor dies attached to a first metallization layer and a plurality of second power semiconductor dies attached to a second metallization layer. A first structured metal frame disposed above the first metallization layer is electrically connected to a load terminal of each first power semiconductor die. A second structured metal frame disposed above the second metallization layer is electrically connected to a load terminal of each second power semiconductor die and to the first metallization layer. A first lead is electrically connected to the second metallization layer. A second lead is electrically connected to the second metallization layer. A third lead interposed between the first and second leads is electrically connected to the first structured metal frame. A fourth lead is electrically connected to the second structured metal frame.

Abstract: An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.

Abstract: A package includes a single integral electrically conductive body, a first chip with an integrated transistor and including a first terminal, a second terminal, and a third terminal, wherein the second terminal and the third terminal are formed on one main surface of the first chip and the first terminal is formed on an opposing main surface of the first chip, and a second chip with an integrated transistor and comprising a fourth, fifth and sixth terminals, wherein the fourth terminal and the sixth terminal are formed on one main surface of the second chip and the fifth terminal is formed on another surface of the second chip, wherein the first chip and the second chip are connected to form a half bridge.

Abstract: A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

Abstract: A method is disclosed. In one example, the method comprises mounting an electronic component on an adhesive base structure on a temporary carrier, and dissolving at least part of the base structure by irradiating the base structure with electromagnetic radiation to thereby release the electronic component.