Patents by Inventor Thorsten Scharf

Thorsten Scharf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210005557
    Abstract: A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 7, 2021
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Meyer, Thomas Behrens, Martin Gruber, Thorsten Scharf, Peter Strobel
  • Patent number: 10886186
    Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: January 5, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Scharf, Ralf Otremba, Thomas Bemmerl, Irmgard Escher-Poeppel, Martin Gruber, Michael Juerss, Thorsten Meyer, Xaver Schloegel
  • Publication number: 20200365553
    Abstract: A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.
    Type: Application
    Filed: April 7, 2020
    Publication date: November 19, 2020
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Meyer, Thomas Behrens, Andreas Grassmann, Martin Gruber, Thorsten Scharf
  • Publication number: 20200328141
    Abstract: A chip package is provided. The chip package includes a semiconductor chip having on a front side a first connecting pad and a second connecting pad, a carrier having a pad contact area and a recess, encapsulation material encapsulating the conductor chip, a first external connection that is free from or extends out of the encapsulation material, an electrically conductive clip, and a contact structure. The semiconductor chip is arranged with its front side facing the carrier with the first connecting pad over the recess and with the second connecting pad contacting the pad contact area. The clip is arranged over a back side of the semiconductor chip covering the semiconductor chip where it extends over the recess. The electrically conductive contact structure electrically conductively connects the first connecting pad with the first external connection.
    Type: Application
    Filed: April 10, 2020
    Publication date: October 15, 2020
    Inventors: Tomasz Naeve, Ralf Otremba, Thorsten Scharf, Markus Dinkel, Martin Gruber, Elvir Kahrimanovic
  • Publication number: 20200321309
    Abstract: Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 8, 2020
    Applicant: Infineon Technologies AG
    Inventors: Petteri Palm, Thorsten Scharf, Ralf Wombacher
  • Patent number: 10777491
    Abstract: A package comprising a carrier, at least one electronic chip mounted on one side of the carrier, an encapsulant at least partially encapsulating the at least one electronic chip and partially encapsulating the carrier, and at least one component attached to an opposing other side of the carrier via at least one contact opening.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 15, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Scharf, Thorsten Meyer
  • Publication number: 20200273790
    Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.
    Type: Application
    Filed: January 21, 2020
    Publication date: August 27, 2020
    Inventors: Bun Kian Tay, Mei Yih Goh, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Thorsten Scharf, Chee Voon Tan
  • Publication number: 20200273781
    Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Inventors: Thorsten Scharf, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Bun Kian Tay
  • Patent number: 10734351
    Abstract: Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Thorsten Scharf, Ralf Wombacher
  • Publication number: 20200227312
    Abstract: A semiconductor device and method is disclosed. In one example, the method includes forming a recess in an electrically insulating encapsulation material, wherein the encapsulation material at least partly encapsulates a semiconductor chip. The method further includes forming an adhesion promoting structure in the recess. The method further includes spraying an electrically conductive material into the recess, wherein the adhesion promoting structure is configured to provide an adhesion between the sprayed electrically conductive material and the encapsulation material.
    Type: Application
    Filed: November 21, 2019
    Publication date: July 16, 2020
    Applicant: Infineon Technologies AG
    Inventors: Irmgard Escher-Poeppel, Thorsten Scharf, Catharina Wille
  • Patent number: 10629575
    Abstract: A semiconductor chip assembly includes first and second semiconductor dies that each include opposite facing upper and lower sides and an outer edge side, and an electrical interposer having opposite facing first and second conductive surfaces and a conductive connection between the conductive surfaces. The second semiconductor die is mounted on top of the first semiconductor die and the interposer such that the lower side of the second semiconductor die faces the first semiconductor die and the interposer, a first lateral section of the second semiconductor die at least partially covers the upper side of the first semiconductor die, and a second lateral section of the second semiconductor die extends past the outer edge side of the first semiconductor die. The first conductive surface is electrically connected to a first terminal that is disposed on a lower side of the second semiconductor die.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 21, 2020
    Assignee: Infineon Techologies AG
    Inventors: Thorsten Scharf, Carsten Ahrens, Helmut Brech, Martin Gruber, Thorsten Meyer, Matthias Zigldrum
  • Publication number: 20200006187
    Abstract: A heat dissipation device includes a first part having a first material and a surface portion, and a second part on the surface portion. The second part has a second material and a porosity.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 2, 2020
    Inventors: Ralf Otremba, Irmgard Escher-Poeppel, Martin Gruber, Michael Juerss, Thorsten Scharf
  • Publication number: 20190333874
    Abstract: A semiconductor device is disclosed. In one example, the semiconductor device comprises a first semiconductor die comprising a first surface, a second surface opposite to the first surface, and a contact pad disposed on the first surface, a further contact pad spaced apart from the semiconductor die, a clip comprising a first layer of a first metallic material and a second layer of a second metallic material different from the first metallic material, wherein the first layer of the clip is connected with the contact pad, and the second layer of the clip is connected with the further contact pad.
    Type: Application
    Filed: April 12, 2019
    Publication date: October 31, 2019
    Applicant: Infineon Technologies AG
    Inventors: Thomas Bemmerl, Martin Gruber, Thorsten Scharf
  • Publication number: 20190304858
    Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 3, 2019
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Scharf, Ralf Otremba, Thomas Bemmerl, Irmgard Escher-Poeppel, Martin Gruber, Michael Juerss, Thorsten Meyer, Xaver Schloegel
  • Publication number: 20190259688
    Abstract: A package comprising a carrier, at least one electronic chip mounted on one side of the carrier, an encapsulant at least partially encapsulating the at least one electronic chip and partially encapsulating the carrier, and at least one component attached to an opposing other side of the carrier via at least one contact opening.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 22, 2019
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Scharf, Thorsten Meyer
  • Patent number: 10366924
    Abstract: A chip carrier includes a redistribution structure, wherein the redistribution structure includes: a dielectric layer extending in a horizontal direction; a first electrically conductive layer arranged over the dielectric layer and extending in the horizontal direction; a trench arranged in the dielectric layer and extending in the horizontal direction; and a filling material filling the trench, wherein the filling material is different from the material of the dielectric layer.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 30, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Scharf, Steffen Jordan
  • Patent number: 10325834
    Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Dirk Meinhold, Frank Daeche, Thorsten Scharf
  • Patent number: 10314238
    Abstract: A block baling press has a bale chamber and a baling ram moveable in the bale chamber in an oscillating manner to compress bale material. An end face of the baling ram facing the bale material is divided into ram segments separated from one another by needle slots. At least a first needle slot is flanked by ram segments with a profiling transverse to the first needle slot. The profiling brings about a weaker compression of the bale material in an edge region of the ram segments adjacent to the first needle slot than in a region of the ram segments spaced apart from the first needle slot. Bales are obtained in which zones of high compression and low compression alternate across the width of the bale chamber. The bales are held together by twine placed around the zones having low compression.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: June 11, 2019
    Assignee: Usines CLAAS France S.A.S.
    Inventors: Ulrich Hesselmann, Thorsten Scharf, Stefan Birkhofer
  • Patent number: 10229891
    Abstract: A package comprising an electronic chip, a laminate-type encapsulant at least partially encapsulating the electronic chip, a wiring structure extending from the electronic chip up to a contact pad, and a completely galvanically formed solderable exterior electric contact electrically coupled with the electronic chip by being arranged on the contact pad.
    Type: Grant
    Filed: February 18, 2017
    Date of Patent: March 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Scharf, Steffen Jordan, Wolfgang Schober, Thomas Ziegler
  • Publication number: 20180358326
    Abstract: Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Applicant: Infineon Technologies AG
    Inventors: Petteri Palm, Thorsten Scharf, Ralf Wombacher