Abstract: A conductive sleeved fastener assembly includes an electrically-conductive fastener having a fastener head and a fastener shank extending from the fastener head and an electrically-conductive fastener sleeve receiving the fastener shank of the fastener and a fastener sleeve flange provided on the fastener sleeve and disposed in direct contact with the fastener head of the fastener. A method of preparing a conductive sleeved fastener for use is also disclosed.

Abstract: A circuit for modeling capacitive coupling comprising a victim line to be tested, a first aggressor line, running alongside the victim line, creating a coupling capacitance between the victim line and the first aggressor line, and a sensor circuit coupled to the victim line, to detect effects of the first aggressor line on the victim line, the sensor circuit measuring timing effects in pseudo-real time.

Abstract: An automated circuitry that can co-exist in any chip and that allows for a accurate characterization of I*R drops at a block and/or whole chip level is described.

Abstract: A circuit including an SRAM cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. EDA tools for such circuits are also provided.

Abstract: A depressed center grinding wheel comprises an abrasive disc. The abrasive disc comprises a working layer, an intermediate layer, a back layer, and at least two reinforcing scrims. The working layer comprises first abrasive particles retained in a first binder material. The first abrasive particles include from 40 to 100 weight percent of first shaped abrasive particles. The back layer comprises second abrasive particles retained in a second binder material. The second abrasive particles include first crushed abrasive particles and are essentially free of shaped abrasive particles. The intermediate layer is disposed between the working layer and the back layer. The intermediate layer comprises third abrasive particles retained in a third binder material. The third abrasive particles include 25 to 75 weight percent of second shaped abrasive particles.

Abstract: A conductive fastener assembly, system, and method are described. The fastener assembly includes a nut having a counterbore formed therein. The counterbore is formed to maintain a sufficient gap between the nut and the protruding end of a fastener sleeve. The nut with the counterbore improves the conductive fastener system such that the need for a solid copper grid and a cap seal is reduced or eliminated.

Abstract: A weight-measuring system for measuring a weight amount of one or more items loaded into a bed of a vehicle is provided. The weight amount can be used to determine whether a weight limit has been exceeded and whether some additional action should be taken. In addition, one type of weight-measuring system is operable under varied conditions, such as rapid weight fluctuations, and is capable of measuring a weight amount when the bed is in various positions (e.g., transporting mode or ground-level, loading mode).

Abstract: A conductive fastener assembly, system, and method, wherein the fastener assembly includes a fastener, a fastener sleeve, a nut, and a lubricant coating. The lubricant coating is deposited on a distal portion of a fastener shank and is omitted from the rest of the fastener. To overcome the stresses placed on the fastener sleeve by the insertion of the fastener shank largely devoid of a lubricant coating, the fastener sleeve is reinforced by one or more of an increased thickness, a high-strength alloy, and a soft metal coating.

Abstract: A circuit including an SRAM cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. EDA tools for such circuits are also provided.

Abstract: Apparatuses, systems and methods for separating heavy hydrocarbons from a solvent stream are disclosed. The heavy hydrocarbons and solvent can be recovered and processed further.

Abstract: There is provided a copolymer having the general structure below, wherein a, b, and d are molar ratios varying between about 0.01 and about 0.90 and c is a molar ratio varying between about 0.01 and about 0.90; A1 represents monomer units comprising a cyano-containing pendant group in which the cyano is not directly attached to the backbone of the copolymer; A2 represents monomer units comprising two or more hydrogen bonding sites; A3 represents monomer units that increase solubility in organic solvents; and A4 represents monomer units that increase solubility in aqueous alkaline solutions. There is also provided a near-infrared radiation-sensitive coating composition comprising this copolymer as well as a positive-working thermal lithographic printing plate comprising a near-infrared radiation-sensitive coating comprising this copolymer, a method of producing such a printing plate, and finally a method of printing using such a printing plate. Formula (I).

Abstract: A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test.

Abstract: A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew.

Abstract: An automated circuitry that can co-exist in any chip and that allows for a accurate characterization of I*R drops at a block and/or whole chip level is described.

Abstract: Energy consumption is reduced within an Internet of Things (IoT) device, without degrading operating performance of the corresponding internal circuitry. A first internal supply voltage (VDDa) used to supply the internal circuitry is reduced from a VDD supply voltage to a lower voltage during an idle state, thereby reducing leakage currents in the internal circuitry. The first internal supply voltage (VDDa) may be reduced to a voltage that is one threshold voltage (Vtp) lower than the VDD supply voltage. A second internal supply voltage (VSSa) used to supply the internal circuitry is increased from the VSS supply voltage to a voltage higher than the VSS supply voltage during the idle state, thereby further reducing leakage currents in the internal circuitry. The second internal supply voltage (VSSa) may be increased to a voltage that is one threshold voltage (Vtn) higher than the VSS supply voltage.

Abstract: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell.

Abstract: A weight-measuring system for measuring a weight amount of one or more items loaded into a bed of a vehicle is provided. The weight amount can be used to determine whether a weight limit has been exceeded and whether some additional action should be taken. In addition, one type of weight-measuring system is operable under varied conditions, such as rapid weight fluctuations, and is capable of measuring a weight amount when the bed is in various positions (e.g., transporting mode or ground-level, loading mode).

Abstract: A conductive fastener assembly, system, and method are described. The fastener assembly includes a nut having a counterbore formed therein. The counterbore is formed to maintain a sufficient gap between the nut and the protruding end of a fastener sleeve. The nut with the counterbore improves the conductive fastener system such that the need for a solid copper grid and a cap seal is reduced or eliminated.

Abstract: A conductive fastener assembly, system, and method, wherein the fastener assembly includes a fastener, a fastener sleeve, a nut, and a lubricant coating. The lubricant coating is deposited on a distal portion of a fastener shank and is omitted from the rest of the fastener. To overcome the stresses placed on the fastener sleeve by the insertion of the fastener shank largely devoid of a lubricant coating, the fastener sleeve is reinforced by one or more of an increased thickness, a high-strength alloy, and a soft metal coating.

Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.