Patents by Inventor Till Schloesser

Till Schloesser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240243130
    Abstract: The disclosure relates to a semiconductor die (1), comprising a vertical power transistor device (2), the vertical power transistor device having a source region (3) and a drain region (4) at opposite sides of a semiconductor body (10), and a lateral transistor device (20), the lateral transistor device having a body region (221) with a lateral channel region (221.1), as well as a source and a drain region formed at a frontside of the semiconductor body, wherein a deep trench (305) is arranged laterally between the vertical power transistor device (2) and the lateral transistor device (20), forming a deep trench isolation (306).
    Type: Application
    Filed: May 11, 2022
    Publication date: July 18, 2024
    Inventors: Andreas Peter Meiser, Till Schlösser, Timothy Henson, Thomas Martin Feil
  • Publication number: 20240210467
    Abstract: One exemplary embodiment relates to a circuit which is integrated into a semiconductor substrate and which comprises a lateral field effect transistor having a drift region and a field plate electrode, which is isolated from the drift region by an isolation zone. The integrated circuit further comprises a first terminal, which is coupled to the field plate electrode, for applying a test voltage to the field plate electrode in a test operating mode. An electronic switch is configured to connect the field plate electrode to a circuit node that is at a reference voltage in a normal operating mode of the integrated circuit. The integrated circuit further comprises a second terminal, which is connected to a control terminal of the electronic switch and is configured to receive a control signal for switching on or off the electronic switch.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 27, 2024
    Inventors: Till Schloesser, Axel Reithofer, Jens Berrenscheen
  • Publication number: 20230246068
    Abstract: A field effect transistor, FET, is proposed. The FET includes a source region of a first conductivity type that is electrically connected to a source electrode at a first surface of a semiconductor body. The FET further includes a drain region of the first conductivity type that is electrically connected to a drain electrode at the first surface. A dielectric structure is arranged between the source region and the drain region along a first lateral direction. The dielectric structure includes a gate dielectric on the first surface and a field dielectric structure having a bottom side below the first surface. The FET further includes a gate electrode on the gate dielectric. The gate electrode and the field dielectric structure are spaced from each other along the first lateral direction. The FET further includes a field electrode having a bottom side below a top side of the field dielectric structure.
    Type: Application
    Filed: January 20, 2023
    Publication date: August 3, 2023
    Inventors: Chi Dong Nguyen, Till Schlösser
  • Patent number: 11705506
    Abstract: A method of manufacturing a semiconductor device includes: forming a trench in a first side of a semiconductor layer, the semiconductor layer including a drift zone of a first conductivity; forming a drain region of the first conductivity type in the first side of the semiconductor layer and laterally adjoining the drift zone; forming a body region of a second conductivity type opposite the first conductivity type and laterally adjoining the drift zone at a side of the drift zone opposite the drain region; and forming source regions of the first conductivity type and body contact regions of the second conductivity type in a sidewall of the trench and arranged in an alternating manner along a length of the trench, using a dopant diffusion process which includes diffusing dopants of both conductivity types from oppositely-doped dopant source layers which are in contact with different regions of the sidewall.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: July 18, 2023
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Andreas Peter Meiser, Till Schloesser
  • Publication number: 20220246744
    Abstract: A transistor device is provided. In an example, the transistor device includes a semiconductor body having a first main surface, a second main surface opposite to the first main surface. The transistor device further includes a transistor cell array including a plurality of transistor cells. The transistor cell array includes a first load electrode over the first main surface. The first load electrode is electrically connected to the plurality of transistor cells. The transistor cell array further includes a second load electrode over the second main surface. The second load electrode is electrically connected to the plurality of transistor cells. The plurality of transistor cells includes at least one control electrode including carbon.
    Type: Application
    Filed: February 1, 2022
    Publication date: August 4, 2022
    Inventors: Ralf Siemieniec, Ingo Muri, Till Schloesser, Hans-Joachim Schulze, Olaf Storbeck
  • Patent number: 11217658
    Abstract: The disclosure relates to a semiconductor device, including a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type on the semiconductor substrate, the second conductivity type being different than the first conductivity type. The semiconductor device also includes an isolation structure electrically isolating a first region of the semiconductor layer from a second region of the semiconductor layer. A shallow trench isolation structure vertically extends from a surface of the semiconductor layer into the first region of the semiconductor layer. An electrical resistor is formed on the shallow trench isolation structure.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: January 4, 2022
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Grzegorz Kozlowski, Till Schloesser
  • Patent number: 11145745
    Abstract: A method for producing a semiconductor component includes: providing a semiconductor body having a first dopant of a first conductivity type; forming a first trench in the semiconductor body starting from a first side; filling the first trench with a semiconductor filler material; forming a superjunction structure by introducing a second dopant of a second conductivity type into the semiconductor body, the semiconductor filler material being doped with the second dopant; forming a second trench in the semiconductor body starting from the first side; and forming a trench structure in the second trench.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: October 12, 2021
    Assignee: Infineon Technologies AG
    Inventors: Till Schloesser, Christian Kampen, Andreas Meiser
  • Publication number: 20210234023
    Abstract: A method of manufacturing a semiconductor device includes: forming a trench in a first side of a semiconductor layer, the semiconductor layer including a drift zone of a first conductivity; forming a drain region of the first conductivity type in the first side of the semiconductor layer and laterally adjoining the drift zone; forming a body region of a second conductivity type opposite the first conductivity type and laterally adjoining the drift zone at a side of the drift zone opposite the drain region; and forming source regions of the first conductivity type and body contact regions of the second conductivity type in a sidewall of the trench and arranged in an alternating manner along a length of the trench, using a dopant diffusion process which includes diffusing dopants of both conductivity types from oppositely-doped dopant source layers which are in contact with different regions of the sidewall.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: Andreas Peter Meiser, Till Schloesser
  • Patent number: 11018244
    Abstract: A method of manufacturing a semiconductor device includes: forming a trench in a first side of a semiconductor layer, the semiconductor layer including a drift zone of a first conductivity; forming a drain region of the first conductivity type in the first side of the semiconductor layer and laterally adjoining the drift zone; forming a body region of a second conductivity type opposite the first conductivity type and laterally adjoining the drift zone at a side of the drift zone opposite the drain region; and forming source regions of the first conductivity type and body contact regions of the second conductivity type in a sidewall of the trench and arranged in an alternating manner along a length of the trench, using a dopant diffusion process which includes diffusing dopants of both conductivity types from oppositely-doped dopant source layers which are in contact with different regions of the sidewall.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 10903079
    Abstract: A method includes: forming first and second trenches in a semiconductor body; forming a first material layer on the semiconductor body in the first and second trenches such that a first residual trench remains in the first trench and a second residual trench remains in the second trench; removing the first material from the second trench; and forming a second material layer on the first material layer in the first residual trench and on the semiconductor body in the second trench. The first material layer includes dopants of a first doping type and the second material layer includes dopants of a second doping type. The method further includes diffusing dopants from the first material layer in the first trench into the semiconductor body to form a first doped region, and from the second material layer in the second trench into the semiconductor body to form a second doped region.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Rolf Weis, Thomas Gross, Hermann Gruber, Franz Hirler, Andreas Meiser, Markus Rochel, Till Schloesser, Detlef Weber
  • Patent number: 10868146
    Abstract: The disclosure relates to a method for producing a semiconductor device. The method includes providing a semiconductor body having first dopants of a first conductivity type and second dopants of a second conductivity type. The method also includes forming a first trench in the semiconductor body via a first mask, and filling the first trench with a semiconductor filling material. The method further includes forming a superjunction structure by introducing a portion of the first dopants from a region of the semiconductor body into the semiconductor filling material, forming a second trench in the semiconductor body via a second mask, which is formed in a manner self-aligned with respect to the first mask, and forming a trench structure in the second trench.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 10700061
    Abstract: A semiconductor device includes a first transistor and a second transistor in a semiconductor substrate. The first transistor includes a first drain contact electrically connected to a first drain region, the first drain contact including a first drain contact portion and a second drain contact portion. The first drain contact portion includes a drain conductive material in direct contact with the first drain region. The second transistor includes a second source contact electrically connected to a second source region. The second source contact includes a first source contact portion and a second source contact portion. The first source contact portion includes a source conductive material in direct contact with the second source region.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Dirk Ahlers, Till Schloesser
  • Publication number: 20200127121
    Abstract: A method of manufacturing a semiconductor device includes: forming a trench in a first side of a semiconductor layer, the semiconductor layer including a drift zone of a first conductivity; forming a drain region of the first conductivity type in the first side of the semiconductor layer and laterally adjoining the drift zone; forming a body region of a second conductivity type opposite the first conductivity type and laterally adjoining the drift zone at a side of the drift zone opposite the drain region; and forming source regions of the first conductivity type and body contact regions of the second conductivity type in a sidewall of the trench and arranged in an alternating manner along a length of the trench, using a dopant diffusion process which includes diffusing dopants of both conductivity types from oppositely-doped dopant source layers which are in contact with different regions of the sidewall.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 23, 2020
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 10629690
    Abstract: A semiconductor device includes a transistor in a semiconductor substrate. The transistor includes a drift zone of a first conductivity type adjacent to a drain region, and a first field plate and a second field plate adjacent to the drift zone. The second field plate is arranged between the first field plate and the drain region. The second field plate is electrically connected to a contact portion arranged in the drift zone. The transistor further includes an intermediate portion of the first conductivity type at a lower doping concentration than the drift zone. A distance between the intermediate portion and the drain region is smaller than the distance between the contact portion and the drain region.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Franz Hirler, Till Schloesser
  • Patent number: 10582580
    Abstract: A switch comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region, the gate electrode being configured to control a conductivity of a channel formed in the body region. The gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction. The body region is adjacent to the source region and the drain region. The switch further comprises a source contact and a body contact portion, the source contact being electrically connected to a source terminal. The body contact portion is in contact with the source contact and is electrically connected to the body region.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Publication number: 20200027969
    Abstract: A method for producing a semiconductor component includes: providing a semiconductor body having a first dopant of a first conductivity type; forming a first trench in the semiconductor body starting from a first side; filling the first trench with a semiconductor filler material; forming a superjunction structure by introducing a second dopant of a second conductivity type into the semiconductor body, the semiconductor filler material being doped with the second dopant; forming a second trench in the semiconductor body starting from the first side; and forming a trench structure in the second trench.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 23, 2020
    Inventors: Till Schloesser, Christian Kampen, Andreas Meiser
  • Publication number: 20190371882
    Abstract: The disclosure relates to a semiconductor device, including a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type on the semiconductor substrate, the second conductivity type being different than the first conductivity type. The semiconductor device also includes an isolation structure electrically isolating a first region of the semiconductor layer from a second region of the semiconductor layer. A shallow trench isolation structure vertically extends from a surface of the semiconductor layer into the first region of the semiconductor layer. An electrical resistor is formed on the shallow trench isolation structure.
    Type: Application
    Filed: May 28, 2019
    Publication date: December 5, 2019
    Inventors: Andreas Meiser, Grzegorz Kozlowski, Till Schloesser
  • Publication number: 20190348525
    Abstract: The disclosure relates to a method for producing a semiconductor device. The method includes providing a semiconductor body having first dopants of a first conductivity type and second dopants of a second conductivity type. The method also includes forming a first trench in the semiconductor body via a first mask, and filling the first trench with a semiconductor filling material. The method further includes forming a superjunction structure by introducing a portion of the first dopants from a region of the semiconductor body into the semiconductor filling material, forming a second trench in the semiconductor body via a second mask, which is formed in a manner self-aligned with respect to the first mask, and forming a trench structure in the second trench.
    Type: Application
    Filed: May 10, 2019
    Publication date: November 14, 2019
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 10468405
    Abstract: An electric circuit includes a semiconductor device. The semiconductor device includes a first transistor and a second transistor in a common semiconductor substrate. The first transistor is of the same conductivity type as the second transistor. A first source region of the first transistor is electrically connected to a first source terminal via a first main surface of the semiconductor substrate. A second drain region of the second transistor is electrically connected to a second drain terminal via a first main surface of the semiconductor substrate. A first drain region of the first transistor and a second source region of the second transistor are electrically connected to an output terminal via a second main surface of the semiconductor substrate. The electric circuit further includes a control circuit operable to control a first gate electrode of the first transistor and a second gate electrode of the second transistor.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: November 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Rainald Sander, Till Schloesser
  • Publication number: 20190287804
    Abstract: A method includes: forming first and second trenches in a semiconductor body; forming a first material layer on the semiconductor body in the first and second trenches such that a first residual trench remains in the first trench and a second residual trench remains in the second trench; removing the first material from the second trench; and forming a second material layer on the first material layer in the first residual trench and on the semiconductor body in the second trench. The first material layer includes dopants of a first doping type and the second material layer includes dopants of a second doping type. The method further includes diffusing dopants from the first material layer in the first trench into the semiconductor body to form a first doped region, and from the second material layer in the second trench into the semiconductor body to form a second doped region.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 19, 2019
    Inventors: Rolf Weis, Thomas Gross, Hermann Gruber, Franz Hirler, Andreas Meiser, Markus Rochel, Till Schloesser, Detlef Weber