Patents by Inventor Timothy B. Cowles

Timothy B. Cowles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030030476
    Abstract: An input buffer receives an external input signal during an active mode and a low-power mode. The input buffer includes a switching system to switch the input buffer between multiple conductive paths such that current consumed by the input buffer during the low-power mode is substantially less than current consumed by the buffer during the active mode.
    Type: Application
    Filed: August 10, 2001
    Publication date: February 13, 2003
    Inventors: Timothy B. Cowles, Victor Wong
  • Publication number: 20030002370
    Abstract: An open digit line memory device includes a memory array. The memory array includes a plurality of memory cells. The memory cells are grouped into sub-arrays. Each of the sub-arrays includes a plurality of digit lines. The digit lines from adjacent sub-arrays connect to a plurality of sense amplifiers. The sense amplifiers located next to the edges of the memory array connect to dummy digit lines. The dummy digit lines are connected to a fixed voltage during a normal mode. During a test mode, the fixed voltage is replaced by a variable voltage so that the all of the sub-arrays, including the sub-arrays at the edges, can be equally stressed during the test mode.
    Type: Application
    Filed: August 29, 2002
    Publication date: January 2, 2003
    Applicant: Micron Technology, Inc.
    Inventor: Timothy B. Cowles
  • Patent number: 6501688
    Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: December 31, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Brendan N. Protzman, Timothy B. Cowles
  • Publication number: 20020191462
    Abstract: A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.
    Type: Application
    Filed: August 29, 2002
    Publication date: December 19, 2002
    Applicant: Micron Technology, Inc.
    Inventors: William Jones, Wen Li, Mark R. Thomann, Timothy B. Cowles, Daniel R. Loughmiller
  • Patent number: 6493286
    Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: December 10, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Brendan N. Protzman, Timothy B. Cowles
  • Publication number: 20020181294
    Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.
    Type: Application
    Filed: April 19, 2002
    Publication date: December 5, 2002
    Inventors: Brendan N. Protzman, Timothy B. Cowles
  • Publication number: 20020181296
    Abstract: A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.
    Type: Application
    Filed: June 5, 2001
    Publication date: December 5, 2002
    Inventors: William Jones, Wen Li, Mark R. Thomann, Timothy B. Cowles, Daniel R. Loughmiller
  • Publication number: 20020181293
    Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.
    Type: Application
    Filed: May 30, 2001
    Publication date: December 5, 2002
    Inventors: Brendan N. Protzman, Timothy B. Cowles
  • Publication number: 20020181295
    Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.
    Type: Application
    Filed: April 19, 2002
    Publication date: December 5, 2002
    Inventors: Brendan N. Protzman, Timothy B. Cowles
  • Publication number: 20020181305
    Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.
    Type: Application
    Filed: April 19, 2002
    Publication date: December 5, 2002
    Inventors: Brendan N. Protzman, Timothy B. Cowles
  • Publication number: 20020181317
    Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.
    Type: Application
    Filed: April 19, 2002
    Publication date: December 5, 2002
    Inventors: Brendan N. Protzman, Timothy B. Cowles
  • Patent number: 6483762
    Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: November 19, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Brendan N. Protzman, Timothy B. Cowles
  • Publication number: 20020167852
    Abstract: An open digit line memory device includes a memory array. The memory array includes a plurality of memory cells. The memory cells are grouped into sub-arrays. Each of the sub-arrays includes a plurality of digit lines. The digit lines from adjacent sub-arrays connect to a plurality of sense amplifiers. The sense amplifiers located next to the edges of the memory array connect to dummy digit lines. The dummy digit lines are connected to a fixed voltage during a normal mode. During a test mode, the fixed voltage is replaced by a variable voltage so that the all of the sub-arrays, including the sub-arrays at the edges, can be equally stressed during the test mode.
    Type: Application
    Filed: May 8, 2001
    Publication date: November 14, 2002
    Applicant: Micron Technology, Inc
    Inventor: Timothy B. Cowles
  • Publication number: 20020133770
    Abstract: A preferred exemplary embodiment of the current invention concerns a memory testing process, wherein circuitry is provided to allow on-chip comparison of stored data and expected data. The on-chip comparison allows the tester to transmit in a parallel manner the expected data to a plurality of chips. In a preferred embodiment, at most one address—and only the column address—corresponding to a failed memory cell is stored in an on-chip address register at one time, with each earlier failed addresses being cleared from the register in favor of a subsequent failed address. Another bit—the “fail flag” bit—is stored in the address register to indicate that a failure has occurred. If the fail flag is present in a chip, that chip is repaired by electrically associating the column address with redundant memory cells rather than the original memory cells. Data concerning available redundant cells may be stored in at least one on-chip redundancy register.
    Type: Application
    Filed: May 24, 2001
    Publication date: September 19, 2002
    Inventors: Timothy B. Cowles, Christian N. Mohr
  • Publication number: 20020133767
    Abstract: A preferred exemplary embodiment of the current invention concerns a memory testing process, wherein circuitry is provided on a chip to allow on-chip comparison of stored data and expected data. The on-chip comparison allows the tester to transmit in a parallel manner the expected data to a plurality of chips. In a preferred embodiment, at most one address—and only the column address—corresponding to a failed memory cell is stored in an on-chip register at one time, with each earlier failed addresses being cleared from the register in favor of a subsequent failed address. Another bit—the “fail flag” bit—is stored in the register to indicate that a failure has occurred. If the fail flag is present in a chip, that chip is repaired by electrically associating the column address with redundant memory cells rather than the original memory cells. Subsequently, the chip's register may be cleared and testing may continue.
    Type: Application
    Filed: March 15, 2001
    Publication date: September 19, 2002
    Inventor: Timothy B. Cowles
  • Publication number: 20020133769
    Abstract: A preferred exemplary embodiment of the current invention concerns memory testing and repair processes, wherein circuitry is provided to allow on-chip comparison of stored data and expected data. The on-chip comparison allows the tester to transmit in a parallel manner the expected data to a plurality of chips. In a preferred embodiment, at most one address—and only the column address—corresponding to a failed memory cell is stored in an on-chip address register at one time, with each earlier failed addresses being cleared from the register in favor of a subsequent failed address. Another bit—the “fail flag” bit—is stored in the address register to indicate that a failure has occurred. If the fail flag is present in a chip, that chip is repaired by electrically associating the column address with redundant memory cells rather than the original memory cells. Data concerning available redundant cells may be stored in at least one on-chip redundancy register.
    Type: Application
    Filed: December 12, 2001
    Publication date: September 19, 2002
    Inventors: Timothy B. Cowles, Christian N. Mohr
  • Publication number: 20020126559
    Abstract: A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode.
    Type: Application
    Filed: January 10, 2002
    Publication date: September 12, 2002
    Inventors: Timothy B. Cowles, Michael A. Shore, Patrick J. Mullarkey
  • Publication number: 20020126560
    Abstract: A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode.
    Type: Application
    Filed: January 10, 2002
    Publication date: September 12, 2002
    Inventors: Timothy B. Cowles, Michael A. Shore, Patrick J. Mullarkey
  • Publication number: 20020126557
    Abstract: A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode.
    Type: Application
    Filed: January 10, 2002
    Publication date: September 12, 2002
    Inventors: Timothy B. Cowles, Michael A. Shore, Patrick J. Mullarkey
  • Publication number: 20020126558
    Abstract: A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode.
    Type: Application
    Filed: January 10, 2002
    Publication date: September 12, 2002
    Inventors: Timothy B. Cowles, Michael A. Shore, Patrick J. Mullarkey