Patents by Inventor Timothy B. Cowles
Timothy B. Cowles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020027824Abstract: In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.Type: ApplicationFiled: August 8, 2001Publication date: March 7, 2002Inventors: Timothy B. Cowles, Jeffrey P. Wright
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Patent number: 6310819Abstract: A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.Type: GrantFiled: October 31, 2000Date of Patent: October 30, 2001Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Jeffrey P. Wright, Hua Zheng
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Publication number: 20010027549Abstract: An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode signal. A method for testing an integrated circuit, the integrated circuit including a first external pin and an input buffer, includes providing a first external input signal to the first external pin at a first specified time, and disabling the input buffer at a second specified time after the first specified time.Type: ApplicationFiled: June 8, 2001Publication date: October 4, 2001Applicant: Micron Technology, Inc.Inventor: Timothy B. Cowles
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Patent number: 6289476Abstract: An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode signal. A method for testing an integrated circuit, the integrated circuit including a first external pin and an input buffer, includes providing a first external input signal to the first external pin at a first specified time, and disabling the input buffer at a second specified time after the first specified time.Type: GrantFiled: June 10, 1998Date of Patent: September 11, 2001Assignee: Micron Technology, Inc.Inventor: Timothy B. Cowles
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Patent number: 6278648Abstract: In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.Type: GrantFiled: April 10, 2000Date of Patent: August 21, 2001Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Jeffrey P. Wright
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Patent number: 6269035Abstract: A semiconductor memory device including a memory-cell array divided into a plurality of memory sub-arrays that are arranged into rows and columns of memory cells. Each of the sub-arrays has a limited number of redundant rows and columns to repair defective memory cells. The redundant memory of at least two memory sub-arrays is coupled to an I/O line through a respective isolation circuit. A control circuit coupled to the isolation circuits selectively couples the redundant memory of the sub-arrays to the I/O line. Coupling the redundant memory of multiple sub-arrays facilitates using the redundant memory of one sub-array to repair the defective memory cells in other sub-arrays also coupled to the I/O line, when the redundant memory primarily associated with the other sub-arrays has been depleted.Type: GrantFiled: October 13, 2000Date of Patent: July 31, 2001Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Victor Wong, James S. Cullum, Jeffrey P. Wright
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Patent number: 6253340Abstract: Systems, methods and apparatus for accessing integrated circuits, such as semiconductor memories and particularly in testing, by reducing the number of clock cycles required to apply sequences of command and address signals to a m-dimensional structure of such integrated circuit, such as a memory array. The system, methods and apparatus comprise structure and steps by which commands are issued responsive to external controls signals and commands are generated independent of such signals, such commands being communicated internal to the integrated circuit via separate data paths.Type: GrantFiled: June 8, 1998Date of Patent: June 26, 2001Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Jeffery P. Wright
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Patent number: 6229749Abstract: A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.Type: GrantFiled: May 17, 2000Date of Patent: May 8, 2001Assignee: Micron Technology Inc.Inventors: Timothy B. Cowles, Jeffrey P. Wright, Hua Zheng
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Patent number: 6212114Abstract: Methods of identifying defects in an array of memory cells and related integrated circuitry are described. In one embodiment, an array of memory cells is provided having a plurality of complementary digit line pairs. The digit line pairs comprise individual digit lines D0n, D0n*, where n>1. The complementary digit line pairs are configured to be placed into different states during sensing operations of the array. A defect-identifying signal is applied to the array by driving both digit lines of at least one digit line pair to a common test state, and the cell plate to another different test state with the use of only one dedicated bus line. In another embodiment, a pair of memory cells is provided each having an access transistor and a capacitor. The capacitor has a cell plate. Write circuitry is operably coupled with the pair of memory cells through respective individual input lines. The write circuitry is configured to write data into the memory cells.Type: GrantFiled: June 1, 2000Date of Patent: April 3, 2001Assignee: Micron Technology, Inc.Inventor: Timothy B. Cowles
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Patent number: 6144593Abstract: A semiconductor memory device including a memory-cell array divided into a plurality of memory sub-arrays that are arranged into rows and columns of memory cells. Each of the sub-arrays have a limited number of redundant rows and columns to repair defective memory cells. The redundant memory of at least two memory sub-arrays are coupled to an I/O line through a respective isolation circuit. A control circuit coupled to the isolation circuits selectively couples the redundant memory of the sub-arrays to the I/O line. Coupling the redundant memory of multiple sub-arrays facilitates using the redundant memory of one sub-array to repair the defective memory cells in other sub-arrays also coupled to the I/O line, when the redundant memory primarily associated with the other sub-arrays have been depleted.Type: GrantFiled: September 1, 1999Date of Patent: November 7, 2000Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Victor Wong, James S. Cullum, Jeffrey P. Wright
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Patent number: 6141290Abstract: A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.Type: GrantFiled: April 13, 1999Date of Patent: October 31, 2000Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Jeffrey P. Wright, Hua Zheng
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Patent number: 6128237Abstract: A method and apparatus for reducing a peak current produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, without reducing the speed of operation of the semiconductor memory device. A memory array includes word lines accessing memory cells and a tracking word line for sequentially activating the sense amplifiers connected to the digit lines by introducing a delay after the activation of each sense amplifier or group of sense amplifiers and before activating the next sense amplifier or group of sense amplifiers, so that the total time for activation of the sense amplifiers for all digit lines associated with an active word line is spread out, but is not longer than the time necessary for activation of an entire word line.Type: GrantFiled: December 6, 1999Date of Patent: October 3, 2000Assignee: Micron Technology, Inc.Inventors: Brian Shirley, Timothy B. Cowles
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Patent number: 6104651Abstract: A method for testing an electronic device includes causing the device to perform an operation. Using circuitry of the device, a duration of time is asynchronously measured in association with the step of causing. The operation is controlled in response to the expiration of the duration.Type: GrantFiled: November 22, 1999Date of Patent: August 15, 2000Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Jeffrey P. Wright
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Patent number: 6094388Abstract: Methods of identifying defects in an array of memory cells and related integrated circuitry are described. In one embodiment, an array of memory cells is provided having a plurality of complementary digit line pairs. The digit line pairs comprise individual digit lines D0.sub.n, D0.sub.n.sup..cndot., where n>1. The complementary digit line pairs are configured to be placed into different states during sensing operations of the array. A defect-identifying signal is applied to the array by driving both digit lines of at least one digit line pair to a common test state, and the cell plate to another different test state with the use of only one dedicated bus line. In another embodiment, a pair of memory cells is provided each having an access transistor and a capacitor. The capacitor has a cell plate. Write circuitry is operably coupled with the pair of memory cells through respective individual input lines. The write circuitry is configured to write data into the memory cells.Type: GrantFiled: July 1, 1999Date of Patent: July 25, 2000Assignee: Micron Technology, Inc.Inventor: Timothy B. Cowles
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Patent number: 6049502Abstract: In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.Type: GrantFiled: August 30, 1999Date of Patent: April 11, 2000Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Jeffrey P. Wright
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Patent number: 6026042Abstract: A method and apparatus for reducing a peak current produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, without reducing the speed of operation of the semiconductor memory device. A memory array includes word lines accessing memory cells and a tracking word line for sequentially activating the sense amplifiers connected to the digit lines by introducing a delay after the activation of each sense amplifier or group of sense amplifiers and before activating the next sense amplifier or group of sense amplifiers, so that the total time for activation of the sense amplifiers for all digit lines associated with an active word line is spread out, but is not longer than the time necessary for activation of an entire word line.Type: GrantFiled: April 10, 1998Date of Patent: February 15, 2000Assignee: Micron Technology, Inc.Inventors: Brian Shirley, Timothy B. Cowles
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Patent number: 5999481Abstract: A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.Type: GrantFiled: August 22, 1997Date of Patent: December 7, 1999Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Jeffrey P. Wright, Hua Zheng
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Patent number: 5995426Abstract: A method for testing an electronic device includes causing the device to perform an operation. Using circuitry of the device, a duration of time is asynchronously measured in association with the step of causing. The operation is controlled in response to the expiration of the duration.Type: GrantFiled: November 4, 1997Date of Patent: November 30, 1999Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Jeffery P. Wright
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Patent number: 5959929Abstract: In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.Type: GrantFiled: December 29, 1997Date of Patent: September 28, 1999Assignee: Micron Technology, Inc.Inventors: Timothy B. Cowles, Jeffrey P. Wright
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Patent number: 5946265Abstract: An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latch a memory address from external address lines and internally generates additional memory addresses. The integrated circuit memory can output data in a continuous stream while new rows of the memory are accessed. A method and circuit are described for outputting a burst of data stored in a first row of the memory while accessing a second row of the memory.Type: GrantFiled: July 11, 1997Date of Patent: August 31, 1999Assignee: Micron Technology, Inc.Inventor: Timothy B. Cowles