Abstract: A lower current input buffer is used for waking up a plurality of higher-current buffers. The lower current buffer monitors a wake-up signal and, when present, enables the higher current buffers. A higher current buffer is used to detect the sleep mode and disable the higher current buffers. A delay circuit may be used to balance the propagation delay through the circuit.

Abstract: In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.

Abstract: A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.

Abstract: A booting circuit, used during antifuse programming, that has a clamping circuit designed to prevent a programming voltage from being unnecessarily limited by other components in an integrated circuit. The booting circuit is connected between an external interface, such as a bond pad, and an internal line, and is activated when the programming voltage is being applied directly to the internal line (i.e., not through the external interface). When activated, the clamping circuit allows a suitable and sufficiently high voltage to be applied to the internal line to properly program the antifuses while also clamping the amount of voltage seen at the external interface.

Abstract: A differential input buffer circuit includes enabling circuitry that provides a first portion of an operating current to an input buffer. Enabling circuitry provides a second portion of the operating current when data is expected. A process may be used in an input buffer that is adapted to draw an operating current. Such a process comprises the acts of providing a first portion of the operating current to the input buffer and providing a second portion of the operating current to the input buffer if the input buffer is expecting data.

Abstract: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

Abstract: A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.

Abstract: A booting circuit, used during antifuse programming, that has a clamping circuit designed to prevent a programming voltage from being unnecessarily limited by other components in an integrated circuit. The booting circuit is connected between an external interface, such as a bond pad, and an internal line, and is activated when the programming voltage is being applied directly to the internal line (i.e., not through the external interface). When activated, the clamping circuit allows a suitable and sufficiently high voltage to be applied to the internal line to properly program the antifuses while also clamping the amount of voltage seen at the external interface.

Abstract: In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.

Abstract: An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode signal. A method for testing an integrated circuit, the integrated circuit including a first external pin and an input buffer, includes providing a first external input signal to the first external pin at a first specified time, and disabling the input buffer at a second specified time after the first specified time.

Abstract: The disclosed embodiments relate to an input buffer circuit that offers relatively high performance and low power consumption. A differential input buffer circuit includes enabling circuitry that provides a first portion of an operating current to an input buffer. Enabling circuitry provides a second portion of the operating current when data is expected.

Abstract: An improved input buffer circuit and method configured for voltage detection is provided that can facilitate use of a mid-level voltage for testing purposes. An exemplary input buffer configured for voltage detection comprises a reference generator and a multi-state detector. The reference generator is configured to generate at least two reference voltages to be provided as input signals to the multi-state detector. The multi-state detector is suitably configured to receive an input reference signal, and through comparison of the input reference signal to the two reference voltages, provide output signals to three output terminals representing a high, low and mid-level state of operation. An exemplary input buffer circuit can comprise two differential pairs of transistors configured in a back-to-back arrangement and sharing a common node, thus resulting in lower current requirements.

Abstract: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

Abstract: A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode.

Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.

Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.

Abstract: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

Abstract: An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.

Abstract: A lower current input buffer is used for waking up a plurality of higher-current buffers. The lower current buffer monitors a wake-up signal and, when present, enables the higher current buffers. A higher current buffer is used to detect the sleep mode and disable the higher current buffers. A delay circuit may be used to balance the propagation delay through the circuit.

Abstract: A signal sharing circuit includes a first pad adapted to receive a signal and a first sharing device associated with a first microelectronic die. The first sharing device is adapted to selectively share the signal with at least a second microelectronic die on one side of the first microelectronic die in response to a first share control signal.