Patents by Inventor Timothy J. McArdle
Timothy J. McArdle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180190768Abstract: A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.Type: ApplicationFiled: December 20, 2017Publication date: July 5, 2018Inventors: Dina H. Triyoso, Timothy J. McArdle, Judson R. Holt, Amy L. Child, George R. Mulfinger
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Patent number: 9953873Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.Type: GrantFiled: May 24, 2016Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Viorel Ontalus, Christopher D. Sheraw, Timothy J. McArdle, Paul Chang
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Patent number: 9893154Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.Type: GrantFiled: May 31, 2017Date of Patent: February 13, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Timothy J. McArdle, Judson R. Holt, Junli Wang
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Publication number: 20170345719Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.Type: ApplicationFiled: May 24, 2016Publication date: November 30, 2017Inventors: Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Viorel Ontalus, Christopher D. Sheraw, Timothy J. McArdle, Paul Chang
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Patent number: 9812453Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include forming a Si fin in a PFET region and a pair of Si fins in a NFET region; forming epitaxial S/D regions; forming a spacer over the S/D region in the PFET region; forming a sacrificial cap over the S/D regions in the NFET region, merging the pair of Si fins; removing the spacer from the S/D region in the PFET region; forming silicide trenches over the S/D regions in the PFET and NEFT regions; implanting dopant into the S/D region in the PFET region while the sacrificial cap protects the S/D regions in the NFET region; removing the sacrificial cap; and forming a metal layer over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region.Type: GrantFiled: February 13, 2017Date of Patent: November 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: George R. Mulfinger, Lakshmanan H. Vanamurthy, Scott Beasor, Timothy J. McArdle, Judson R. Holt, Hao Zhang
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Publication number: 20170294515Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.Type: ApplicationFiled: May 31, 2017Publication date: October 12, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Timothy J. MCARDLE, Judson R. HOLT, Junli WANG
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Patent number: 9768288Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.Type: GrantFiled: August 15, 2016Date of Patent: September 19, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jack O. Chu, Christos D. Dimitrakopoulos, Alfred Grill, Timothy J. McArdle, Dirk Pfeiffer, Katherine L. Saenger, Robert L. Wisnieff
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Patent number: 9722045Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.Type: GrantFiled: October 23, 2015Date of Patent: August 1, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Bhupesh Chandra, Viorel Ontalus, Timothy J. McArdle, Paul Chang, Claude Ortolland, Judson R. Holt
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Patent number: 9698226Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.Type: GrantFiled: April 11, 2016Date of Patent: July 4, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Timothy J. McArdle, Judson R. Holt, Junli Wang
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Publication number: 20170186881Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.Type: ApplicationFiled: August 15, 2016Publication date: June 29, 2017Inventors: JACK O. CHU, CHRISTOS D. DIMITRAKOPOULOS, ALFRED GRILL, TIMOTHY J. McARDLE, DIRK PFEIFFER, KATHERINE L. SAENGER, ROBERT L. WISNIEFF
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Publication number: 20170117387Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.Type: ApplicationFiled: October 23, 2015Publication date: April 27, 2017Inventors: Bhupesh Chandra, Viorel Ontalus, Timothy J. McArdle, Paul Chang, Claude Ortolland, Judson R. Holt
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Publication number: 20170033181Abstract: One illustrative method disclosed herein includes, among other things, individually forming alternating layers of different semiconductor materials in a substrate fin cavity so as to form a multi-layer fin above a recessed substrate fin, wherein each of the layers of different semiconductor materials is formed to a final thickness that is less than a critical thickness of the layer of different semiconductor material being formed, recessing the layer of insulating material so as to expose at least a portion of the multi-layer fin above a recessed upper surface of the layer of insulating material and forming a gate structure around at least a portion of the of exposed the multi-layer fin.Type: ApplicationFiled: July 28, 2015Publication date: February 2, 2017Inventors: Timothy J. McArdle, Judson R. Holt, Bharat V. Krishnan, Jody A. Fronheiser
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Patent number: 9466616Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.Type: GrantFiled: February 26, 2016Date of Patent: October 11, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Eric C. T. Harley, Judson R. Holt, Yue Ke, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek
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Publication number: 20160181285Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.Type: ApplicationFiled: February 26, 2016Publication date: June 23, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Eric C.T. Harley, Judson R. Holt, Yue Ke, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek
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Publication number: 20160163707Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.Type: ApplicationFiled: February 5, 2016Publication date: June 9, 2016Inventors: Kangguo Cheng, Eric C.T. Harley, Judson R. Holt, Gauri V. Karve, Yue Ke, Derrick Liu, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek, Melissa Alyson Smith
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Patent number: 9318608Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.Type: GrantFiled: September 29, 2014Date of Patent: April 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Eric C. T. Harley, Judson R. Holt, Yue Ke, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek
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Publication number: 20160093740Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.Type: ApplicationFiled: September 29, 2014Publication date: March 31, 2016Inventors: Eric C. T. Harley, Judson R. Holt, Yue Ke, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek
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Patent number: 9287399Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: GrantFiled: October 7, 2014Date of Patent: March 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Patent number: 9287264Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.Type: GrantFiled: December 5, 2014Date of Patent: March 15, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Kangguo Cheng, Eric C. T. Harley, Judson R. Holt, Gauri V. Karve, Yue Ke, Derrick Liu, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek, Melissa A. Smith
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Patent number: 9236250Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.Type: GrantFiled: June 21, 2013Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Jack O. Chu, Christos D. Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Robert L. Wisnieff