Patents by Inventor Timothy J. McArdle
Timothy J. McArdle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9236477Abstract: Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions.Type: GrantFiled: February 17, 2014Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Jack O. Chu, Christos Dimitrakopoulos, Eric C. Harley, Judson R. Holt, Timothy J. McArdle, Matthew W. Stoker
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Publication number: 20150270332Abstract: A method of forming a semiconductor structure includes forming a first fin and a second fin on a substrate. A gate structure is formed over a first portion of the first fin and the second fin without covering a second portion of the first fin and the second fin. Single-crystal epitaxial layers are deposited surrounding the second portion of the first fin and the second fin such that the single-crystal epitaxial layer on the first fin does not contact the single-crystal epitaxial layer on the second fin. A polycrystalline layer is then deposited surrounding the single-crystal epitaxial layers, so that the polycrystalline layer contacts the single-crystal epitaxial layer on the first fin and the single-crystal epitaxial layer on the second fin. The single-crystal epitaxial layers and the polycrystalline layer form a merged source-drain region.Type: ApplicationFiled: March 24, 2014Publication date: September 24, 2015Applicant: International Business Machines CorporationInventors: Eric C. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Timothy J. McArdle, Alexander Reznicek, Dominic J. Schepis
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Patent number: 9123826Abstract: A method of forming a semiconductor structure includes forming a first fin and a second fin on a substrate. A gate structure is formed over a first portion of the first fin and the second fin without covering a second portion of the first fin and the second fin. Single-crystal epitaxial layers are deposited surrounding the second portion of the first fin and the second fin such that the single-crystal epitaxial layer on the first fin does not contact the single-crystal epitaxial layer on the second fin. A polycrystalline layer is then deposited surrounding the single-crystal epitaxial layers, so that the polycrystalline layer contacts the single-crystal epitaxial layer on the first fin and the single-crystal epitaxial layer on the second fin. The single-crystal epitaxial layers and the polycrystalline layer form a merged source-drain region.Type: GrantFiled: March 24, 2014Date of Patent: September 1, 2015Assignee: International Business Machines CorporationInventors: Eric C. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Timothy J. McArdle, Alexander Reznicek, Dominic J. Schepis
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Publication number: 20150236147Abstract: Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions.Type: ApplicationFiled: February 17, 2014Publication date: August 20, 2015Applicant: International Business Machines CorporationInventors: Jack O. Chu, Christos Dimitrakopoulos, Eric C. Harley, Judson R. Holt, Timothy J. McArdle, Matthew W. Stoker
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Publication number: 20150084096Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: ApplicationFiled: October 7, 2014Publication date: March 26, 2015Inventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Patent number: 8940595Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: GrantFiled: March 15, 2013Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Rao Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Publication number: 20140374702Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.Type: ApplicationFiled: September 8, 2014Publication date: December 25, 2014Inventors: JACK O. CHU, CHRISTOS D. DIMITRAKOPOULOS, ALFRED GRILL, TIMOTHY J. McARDLE, DIRK PFEIFFER, KATHERINE L. SAENGER, ROBERT L. WISNIEFF
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Patent number: 8877340Abstract: A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.Type: GrantFiled: July 27, 2010Date of Patent: November 4, 2014Assignee: International Business Machines CorporationInventors: Jack O. Chu, Christos Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Chun-Yung Sung, Robert L. Wisnieff
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Publication number: 20140264558Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Rao Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Patent number: 8828762Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.Type: GrantFiled: October 18, 2012Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Jack O. Chu, Christos D. DiMitrakopoulos, Alfred Grill, Timothy J. McArdle, Dirk Pfeiffer, Katherine L. Saenger, Robert L. Wisnieff
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Patent number: 8759824Abstract: A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.Type: GrantFiled: January 4, 2013Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Christos D. Dimitrakopoulos, Alfred Grill, Timothy J. McArdle
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Patent number: 8658488Abstract: A graphene layer is provided onto at least an upper surface of a first dielectric material which includes at least one first conductive region contained therein. At least one semiconductor device is formed using the graphene layer as an element of the at least one semiconductor device. After forming the at least one semiconductor device, a second dielectric material is formed covering the graphene layer, the at least one semiconductor device, and portions of the first dielectric material. The second dielectric that is formed includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one semiconductor device.Type: GrantFiled: March 14, 2013Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Christos D. Dimitrakopoulos, Guy Cohen, Stephen M. Gates, Alfred Grill, Timothy J. McArdle, Chun-yung Sung
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Publication number: 20130285014Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.Type: ApplicationFiled: June 21, 2013Publication date: October 31, 2013Inventors: Jack O. Chu, Christos D. Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Robert L. Wisnieff
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Patent number: 8541769Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.Type: GrantFiled: November 9, 2010Date of Patent: September 24, 2013Assignee: International Business Machines CorporationInventors: Jack O. Chu, Christos D. Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Robert L. Wisnieff
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Patent number: 8476617Abstract: A semiconductor structure having a high Hall mobility is provided that includes a SiC substrate having a miscut angle of 0.1° or less and a graphene layer located on an upper surface of the SiC substrate. Also, provided are semiconductor devices that include a SiC substrate having a miscut angle of 0.1° or less and at least one graphene-containing semiconductor device located atop the SiC substrate. The at least one graphene-containing semiconductor device includes a graphene layer overlying and in contact with an upper surface of the SiC substrate.Type: GrantFiled: February 18, 2011Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Christos D. Dimitrakopoulos, Alfred Grill, Timothy J. McArdle, John A. Ott, Robert L. Wisnierff
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Patent number: 8440999Abstract: A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.Type: GrantFiled: February 15, 2011Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Christos D. Dimitrakopoulos, Guy M. Cohen, Stephen M. Gates, Alfred Grill, Timothy J. McArdle, Chun-yung Sung
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Patent number: 8354296Abstract: A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.Type: GrantFiled: January 19, 2011Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Christos D. Dimitrakopoulos, Alfred Grill, Timothy J. McArdle
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Publication number: 20120319078Abstract: A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.Type: ApplicationFiled: August 28, 2012Publication date: December 20, 2012Applicant: International Business Machines CorporationInventors: Jack O. Chu, Christos Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Chun-Yung Sung, Robert L. Wisnieff
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Publication number: 20120211723Abstract: A semiconductor structure having a high Hall mobility is provided that includes a SiC substrate having a miscut angle of 0.1° or less and a graphene layer located on an upper surface of the SiC substrate. Also, provided are semiconductor devices that include a SiC substrate having a miscut angle of 0.1° or less and at least one graphene-containing semiconductor device located atop the SiC substrate. The at least one graphene-containing semiconductor device includes a graphene layer overlying and in contact with an upper surface of the SiC substrate.Type: ApplicationFiled: February 18, 2011Publication date: August 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christos D. Dimitrakopoulos, Alred Grill, Timothy J. McArdle, John A. Ott, Robert L. Wisnierff
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Publication number: 20120205626Abstract: A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.Type: ApplicationFiled: February 15, 2011Publication date: August 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christos D. Dimitrakopoulos, Guy M. Cohen, Stephen M. Gates, Alfred Grill, Timothy J. McArdle, Chun-Yung Sung