Abstract: A method for forming thin film transistor with lateral crystallization. The method at least includes the following steps. First of all, an insulation substrate is provided. Then, an amorphous silicon layer is provided on the insulation substrate. The seeds are formed by annealing a portion of the amorphous silicon layer by excimer laser system, and the lateral-growth grain is formed by using the seeds to grow laterally by annealing the amorphous silicon layer, wherein the amorphous silicon layer defines an active region. Then, sequentially a dielectric layer and a polysilicon layer is deposited on the active region, wherein the dielectric layer and the polysilicon layer are gate electrodes, a gate is defined on the substrate, and the polysilicon layer is formed by etching. Next, source and drain regions are formed by implanting numerous ions into amorphous silicon layer by using the gate electrode as a mask.

Abstract: A post-processing treatment of a low dielectric constant material. In the post-processing treatment, a shallow implantation is conducted to form a shallow compact layer over a dielectric film. This shallow compact surface layer acts as a barrier that prevents the absorption of moisture by the dielectric film. The shallow implantation is carried out using boron ions at an energy level of between about 10 and 50 keV and a dosage of between about 1×1015 atm/cm2 and 1×1016 atm/cm2.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.

Abstract: A method of forming a polysilicon thin film transistor. An amorphous silicon channel layer is formed over an insulating substrate. An active region is patterned out in the amorphous silicon channel layer. An oxide layer and a gate electrode are sequentially formed over the amorphous silicon channel layer. A lightly doped source/drain region is formed in the amorphous silicon channel layer and then a spacer is formed over the gate electrode. A source/drain region is formed in the amorphous silicon channel layer. A portion of the oxide layer above the source/drain region is removed. An isolation spacer is formed on the sidewalls of the spacer. A self-aligned silicide layer is formed at the top section of the spacer and the source/drain region. Finally, a metal-induced lateral crystallization process is conducted to transform the amorphous silicon channel layer into a lateral-crystallization-polysilicon channel layer.

Abstract: A process of forming a low dielectric constant (low k) material is disclosed. The process of the present invention comprises introducing silane (SinH2n+2) and fluorocarbon (CmF2m+2) gases, where n=1 to 3 and m=1 to 3, into a chemical vapor deposition (CVD) chamber, thus forming a low dielectric material layer on a substrate having semiconductor devices by the CVD process. An in situ Argon annealing process is then performed in the chamber. The process of the present invention produces a layer having a dielectric constant of 2.5 and good thermal stability.

Abstract: A method of forming an unlanded via. A substrate having a conductive wire thereon is provided. An etching stop spacer is formed on each sidewall of the conductive wire. An inter-metal dielectric layer is formed over the substrate. The inter-metal dielectric layer is patterned to form a via opening that exposes the conductive wire and then a metal plug that occupies the entire via hole is formed.

Abstract: A structure for forming thin film transistor with reduced metal impurities. The structure at least includes the following steps. First of all, an insulation substrate. Then, an insulating gettering layer on the insulation substrate, wherein the amorphous silicon layer defines an active area, and a channel region on the insulating gettering layer, a source region on the insulating gettering layer adjacent to the channel region, a drain region on the insulating gettering layer adjacent to the channel region and opposite to the source region, and a gate on the channel region, wherein the source, drain, insulating gettering layer and channel region are components of a transistor.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes providing a substrate having metallic lines thereon. A high molecular weight sacrificial film is formed over the substrate. A portion of the high molecular weight sacrificial layer is removed to form spacers. A dielectric layer is formed over the substrate, the top surface of the metallic lines and the spacers. Finally, a thermal dissociation operation is conducted to remove the spacers, thereby forming an air pocket on each sidewall of the metallic lines.

Abstract: A low temperature polysilicon manufacturing method. A system for performing physical vapor deposition is used to form an amorphous silicon film with micro-crystals therein. The amorphous silicon film is annealed at a temperature between 400° C. to 500° C. for about 6 to 16 hours to form a polysilicon film. The polysilicon film can be further processed into a low-temperature polysilicon film transistor.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.

Abstract: A method for fabricating a noble metal electrode of a capacitor. A substrate having a doped region is provided. A dielectric layer is formed to cover the substrate including the doped region with a contact is penetrating through the dielectric layer to couple with the doped region. A barrier layer is formed to cover the dielectric layer and the contact. A polysilicon layer is formed on the barrier layer. The polysilicon layer and TiN barrier layer are etched to form an electrode pattern. The chip is immersed in a solution having noble metal ions and reducing agent for the noble metal ions. In such solution, a displacement reaction takes place to displace the polysilicon layer by a noble metal layer. After the immersion step, the chip is annealed to densify the noble metal layer.

Abstract: A method of increasing a surface area of a bottom electrode for a DRAM. A polysilicon layer is formed. An etching process is performed and the polysilicon layer is etched into a surface having protrusions in order to increase the surface area of the polysilicon layer. A redox reaction is performed and the etched polysilicon layer is transformed to a metal layer by use of a solution; thus, the original appearance is still maintained. An annealing process is performed to concentrate the metal layer and further to reduce a thin-film leakage current.

Abstract: A structure of a stacked barrier layer is provided. A first titanium layer is formed on a semiconductor substrate using plasma enhanced chemical vapor deposition (PECVD). At least a stacked barrier layer is formed on the first titanium layer. The stacked barrier layer includes a first titanium nitride layer and a plasma treated titanium nitride layer. The plasma treated titanium nitride layer is treated using a plasma gas including ammonia gas and nitrogen gas.

Abstract: A method for improving a characteristic of a dielectric material. A methylsilsesquioxane having a low dielectric constant is used as a dielectric material. A methylsilsesquioxane film is formed on a substrate. A baking process is performed on the methylsilsesquioxane film, and then a curing process is performed on the methylsilsesquioxane film. Next, a hydrogen plasma treatment is performed on the surface of the methylsilsesquioxane film to prevent the methylsilsesquioxane film from being damaged by oxygen plasma for removing photoresist layer, so that the characteristically low dielectric constant of the methylsilsesquioxane film is maintained.

Abstract: A method of fabricating a DRAM capacitor. A silicon germanium layer is formed on a lower electrode of the capacitor. The silicon germanium layer is oxidized to form a segregated grained germanium layer and a silicon oxide layer where the segregated grained germanium is distributed on the lower electrode. The silicon oxide layer is then removed. Using the segregated grained germanium as a hard mask, the lower electrode is etched to a depth to form a multi-cylinder structure. The segregated grained germanium is then removed. A capacitor dielectric layer and an upper electrode are successively formed on the multi-cylinder structure.

Abstract: A method of fabricating a static random access memory. A gate oxide layer is formed on a substrate having active regions of an access transistor and a drive transistor. A Polysilicon layer is formed on the gate oxide layer. A germanium implantation is performed on the polysilicon layer of the active region of the drive region to form a polysilicon germanium layer. Thereafter, the polysilicon layer and the polysilicon germanium layer are patterned to form a poly gate and a polysilicon germanium gate on the active regions of the access transistor and the drive transistor. A lightly doped region is formed in the substrate beside the gates. A spacer is then formed on the sidewall of the gates. A heavily doped region is formed in the substrate beside the spacer.

Abstract: A method of manufacturing a method of manufacturing a thin film transistor. An aluminum gate electrode is formed on a substrate. A protective layer is formed on the top surface and the sidewall of the aluminum gate electrode. A gate dielectric layer is formed on the substrate and the protective layer. An intrinsic amorphous-silicon thin film is formed on the gate dielectric layer. A heavily doped amorphous-silicon thin film is formed on the intrinsic amorphous-silicon thin film. A patterned source/drain conductive layer is formed on the heavily doped amorphous-silicon thin film to expose a portion of the heavily doped amorphous-silicon thin film. The portion of the heavily doped amorphous-silicon thin film exposed by the patterned source/drain conductive layer is removed to expose a portion of the intrinsic amorphous-silicon thin film.

Abstract: The invention provides a method for manufacturing a transistor having a low leakage current. In general, spacers must be formed to isolate a gate from a subsequently-formed drain, thereby reducing a leakage current. In the invention, the spacers are formed on the vertical sides of the gate by using a selective deposition process. Therefore, the method for manufacturing a transistor having a low leakage current according to the invention not only constitutes a simplified process, but also controls the widths of the spacers precisely, so that the leakage current of the transistor can be greatly decreased.

Abstract: A method to form a TFT includes providing an insulating substrate. An amorphous silicon layer, a first polysilicon layer, an oxide layer, a second polysilicon layer are sequentially formed on the insulating substrate and are patterned to form an active region. On the active region, there are a desired gate region, and a desired interchangeable source/drain region. A portion of the second polysilicon, the oxide layer, the first polysilicon layer above the desired interchangeable source/drain region are removed, and a top portion of the amorphous-Si layer with a depth is also removed. The remaining portion of the a-Si layer is converted into a conductive layer through, for example, laser crystallization method so as to serve as the interchangeable source/drain region.

Abstract: A method for forming a planarized dielectric layer comprising the steps of first dissolving hydrogen silsesquoxane (HSQ) in a solvent to form a solution, then spreading the solution over a silicon substrate. Next, the solvent is allowed to evaporate, and then heated-treated using a temperature of between 150.degree. C. to 400.degree. C. to form a silica-coated dielectric layer. Finally, a fluoride implant treatment (FIT) is performed to create a dielectric layer having a better thermal stability, more stable dielectric constant and a lower leakage current.