Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.

Abstract: The invention relates to a method for directly patterning a low-k dielectric layer by a high energy flow without using any photoresist layer, so that the exposed portion of the low-k dielectric layer is cured and becomes insoluble to the developing solution. The unexposed portion of the low-k dielectric layer remains soluble to the developing solution and will be removed in the developing process. The performance and reliability of the devices are improved and the fabrication processes are simplified.

Abstract: The present invention is a method to avoid deterioration of a dielectric characteristic of a dielectric layer having a low dielectric constant (low k) during a stripping process. The method involves first forming a low k dielectric layer on the surface of a substrate of a semiconductor wafer. Then, a patterned photoresist layer is formed over the surface of the low k dielectric layer. The patterned photoresist layer is then used as a hard mask to perform an etching process on the low k dielectric layer. A stripping process is then performed to remove the patterned photoresist layer. Finally, a surface treatment is utilized on the low k dielectric layer to remove Si—OH bonds in the low k dielectric layer so as to avoid moisture absorption of the low k dielectric layer that causes deterioration of the dielectric characteristic.

Abstract: The present invention provides a method to form a self-aligned MOS transistor with a gate capped by a metal silicide layer. The gate has a larger surface area and a lower resistance, so this method is suitable as the feature size of integral circuits scale down. In this method, the primary step is to deposit a selective dielectric layer, such as polysilicon germanium layer, on the top of a gate to increase the surface area of the gate. Then, a metal silicide layer is formed on the surface of the dielectric layer to decrease the resistance of the gate. Therefore, comparing to conventional methods, a gate formed by the present method has a larger contacting area and is more ease to connect to a conductive line, so that the performance of a MOS transistor can be improved.

Abstract: The present invention provides a method for fabricating a low dielectric constant (low-k) material film. A spin-on low-k material film is formed in a provided substrate, and a baking process is performed to the spin-on low-k material film. An energy beam is then applied evenly on the spin-on low-k material film to cure the film. The present invention can efficiently reduce leakage currents of the low-k material film by applying high-energy beams onto the low-k material to attain complete bindings.

Abstract: A method of repairing a low dielectric constant (low k) material layer starts with coating a photoresist layer on the low k material layer on a semiconductor wafer. After transferring a pattern of the photoresist layer to the low k material layer, an oxygen plasma ashing process is performed to remove the photoresist layer. Finally, by contacting the low k material layer with a solution of alkyl silane comprising an alkyl group and halo substituent, Si—OH bonds formed in the low k layer during the oxygen plasma ashing process are removed so as to repair damage to the low k material layer caused by the oxygen plasma ashing process, and to enhance a surface of the low k material layer to a hydrophobic surface to prevent moisture adhering to the surface of the low k material layer.

Abstract: A low k dielectric layer is formed on a surface of a substrate of a semiconductor wafer. Then, a surface treatment is performed to the low k dielectric layer to form a passivation layer on a surface of the low k dielectric layer. A patterned photoresist layer is formed over the surface of the semiconductor wafer. The patterned photoresist layer is then used as a hard mask to perform an etching process on the low k dielectric layer. Finally, a stripping process is performed to remove the patterned photoresist layer. The passivation layer is used to prevent deterioration of the dielectric characteristic of the low k dielectric layer during the stripping process.

Abstract: A low dielectric constant (low k) material layer is positioned on a semiconductor wafer. A first hydrogen-containing plasma treatment is performed to reinforce a surface of the low k material layer against corrosion caused by a photoresist stripper. A photoresist layer, having an opening in the photoresist layer to expose portions of the low k material layer, is then coated on the low k material layer. By dry etching the low k material layer through the opening, a pattern in the photoresist layer is transferred to the low k material layer. An ashing process with an oxygen plasma supply is then performed to ash the photoresist layer. Finally, the semiconductor wafer is dipped in a wet stripper to completely remove the photoresist layer.

Abstract: The present invention is a method to avoid deterioration of a dielectric characteristic of a dielectric layer having a low dielectric constant (low k) during a stripping process. The method involves first forming a low k dielectric layer on the surface of a substrate of a semiconductor wafer. Then, a patterned photoresist layer is formed over the surface of the low k dielectric layer. The patterned photoresist layer is then used as a hard mask to perform an etching process on the low k dielectric layer. A stripping process is then performed to remove the patterned photoresist layer. Finally, a surface treatment is utilized on the low k dielectric layer to remove Si—OH bonds in the low k dielectric layer so as to avoid moisture absorption of the low k dielectric layer that causes deterioration of the dielectric characteristic.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.

Abstract: A method for forming thin film transistor with reduced metal impurities. The method at least includes the following steps. First of all, an insulation substrate is provided, and an insulating gettering layer is deposited on the substrate, and an amorphous silicon layer is deposited on the insulating gettering layer, wherein the amorphous silicon layer defines an active area. Then, a channel region is formed by using metal induced laterally crystallization process, and sequentially a dielectric layer and a polysilicon layer are deposited on the channel region, wherein the dielectric layer and the polysilicon layer are gate electrode. Finally, implanting numerous ions into amorphous silicon layer by using the gate electrode as a mask to form source and drain regions.

Abstract: A method for manufacturing a hydrogen gas sensor is provided. A silicon layer with a rugged surface is formed on a dielectric layer over a first conductive electrode on a semiconductor substrate. The whole semiconductor substrate is placed in an aqueous solution containing metal ions in order that the silicon atoms of the silicon layer are substituted for the metal ions in the aqueous solution by a non-electroplating reduction-oxidation reaction. The result is a deposit of a metal layer having a rugged surface formed on the dielectric layer to serve as a second conductive electrode.

Abstract: A method of forming a polysilicon thin film transistor. An amorphous silicon channel layer is formed over an insulating substrate. An active region is patterned out in the amorphous silicon channel layer. An oxide layer and a gate electrode are sequentially formed over the amorphous silicon channel layer. A lightly doped source/drain region is formed in the amorphous silicon channel layer and then a spacer is formed over the gate electrode. A source/drain region is formed in the amorphous silicon channel layer. A portion of the oxide layer above the source/drain region is removed. An isolation spacer is formed on the sidewalls of the spacer. A self-aligned silicide layer is formed at the top section of the spacer and the source/drain region. Finally, a metal-induced lateral crystallization process is conducted to transform the amorphous silicon channel layer into a lateral-crystallization-polysilicon channel layer.

Abstract: A method for forming silicon dioxide-low k dielectric stack is provided. The present invention is characterized in that applying H2 plasma on a low k dielectric layer formed on a conductive interconnect layer to cover dangling bonds on the surface of the low k dielectric layer. Thereby, preventing the reaction between the low k dielectric layer and oxygen gas employed in a subsequent process for forming a cap layer of silicon dioxide occurring, and thus prohibiting oxygen gas damaging the low k dielectric layer.

Abstract: A method of forming a polysilicon thin film transistor. An amorphous silicon channel layer is formed over an insulating substrate. An active region is patterned out in the amorphous silicon channel layer. An oxide layer and a gate electrode are sequentially formed over the amorphous silicon channel layer. A lightly doped source/drain region is formed in the amorphous silicon channel layer and then a spacer is formed over the gate electrode. A source/drain region is formed in the amorphous silicon channel layer. A portion of the oxide layer above the source/drain region is removed. An isolation spacer is formed on the sidewalls of the spacer. A self-aligned silicide layer is formed at the top section of the spacer and the source/drain region. Finally, a metal-induced lateral crystallization process is conducted to transform the amorphous silicon channel layer into a lateral-crystallization-polysilicon channel layer.

Abstract: The present invention provides a method for fabricating a metal-oxide-semiconductor (MOS) transistor on the surface of a semiconductor wafer. The present method first forms a stacked structure comprising a dielectric layer, a doped polysilicon layer, and a sacrificial layer, respectively, in the active area of the surface of the semiconductor wafer. Next, two lightly doped drains are then formed adjacent to the stacked structure. A spacer is then formed around the stacked structure, followed by an ion implantation process to form a source and drain of the MOS transistor. Then, the sacrificial layer is removed to form a trough with the spacer and the doped polysilicon layer. A self-aligned silicide (salicide) process is then performed to form a silicide layer on the surface of the source, drain, and doped polysilicon layer. Finally, a tungsten (W) layer is formed on the surface of each silicide layer and filling the trough to complete the fabrication of the MOS transistor according to the present invention.

Abstract: A method for forming thin film transistor with lateral crystallization. The method at least includes the following steps. First of all, an insulation substrate is provided. Then, an amorphous silicon layer is provided on the insulation substrate. The seeds are formed by annealing a portion of said amorphous silicon layer by excimer laser system, and the lateral-growth grain is formed by using the seeds to grow laterally by annealing the amorphous silicon layer, wherein the amorphous silicon layer defines an active region. Then, sequentially a dielectric layer and a polysilicon layer is deposited on the active region, wherein the dielectric layer and the polysilicon layer are gate electrode, a gate is defined on the substrate, and the polysilicon layer is formed by etching. Next, source and drain regions are formed by implanting numerous ions into amorphous silicon layer by using the gate electrode as a mask.

Abstract: A method of chemical mechanical polishing organic silicon material with a low dielectric constant. An oxygen plasma treatment is performed on an organic silicon material with a low dielectric constant, so that the carbon contained in the organic silicon material is removed. A chemical mechanical polishing step is performed to planarize the organic silicon material after the oxygen plasma treatment. A ammonia plasma treatment is further performed to mend the damaged portion of the organic silicon material.

Abstract: A method for forming shallow junction, at least includes following steps: provides a substrate; forms a dielectric layer and a conductor layer in sequence on the substrate; removes part of the conductor layer and part of the dielectric layer to form a gate on the substrate; forms a spacer on the sidewall of the gate; forms a poly-silicon-germanium layer on the bare surface of the substrate and the top of the gate; implants numerous ions into the poly-silicon-germanium layer and forms a metal layer on both the poly-silicon-germanium layer and the spacer; performs a thermal process; and removes residual the metal layer. Whereby, the sequences for ions implantation and formation of poly-silicon-germanium layer are exchangeable.

Abstract: A chemical mechanical polishing slurry comprising: a nitric acid solution; a weak acid solution, wherein mollar concentration of for weak acid acqeous solution is less than mollar concentration of for nitric acid acqeous solution; and an abrasive. Also, a method for polishing a substrate including at least one metal layer, comprising: mixing a nitric acid solution, a weak acid solution, an abrasive and a solvent to form a chemical mechanical polishing slurry; applying for chemical mechanical polishing slurry to for substrate; and bringing a pad into contact with for substrate and moving for pad in relation to for substrate to remove a portion of for metal layer.