Abstract: A buried gate structure and a method for forming the same are provided. The structure includes first and second gate dielectric layers respectively formed on the surface of the lower portion and the surface of the upper portion of a gate trench of the semiconductor substrate. The structure includes a first gate electrode formed on the first gate dielectric layer. The structure includes an insulating cap layer formed on the first gate electrode to fill the remaining space of the gate trench. The first gate dielectric layer includes a negative capacitance dielectric material. The second gate dielectric layer includes a different dielectric material than the negative capacitance dielectric material. The interface between the first gate dielectric layer and the second gate dielectric layer is lower than the bottom surfaces of the source region and the drain region of the semiconductor substrate.

Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

Abstract: Semiconductor devices and methods of fabrication are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin and into a substrate as an initial step in forming a source/drain region. A first semiconductor material is epitaxially grown from channels exposed along sidewalls of the opening to form first source/drain structures. A second semiconductor material is epitaxially grown from the first semiconductor material to form a second source/drain structure over and to fill a space between the first source/drain structures. A bottom of the second source/drain structure is located below a bottommost surface of the first source/drain structures. The second semiconductor material has a greater concentration percentage by volume of germanium than the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.

Abstract: The present disclosure provides an embodiment of a method. The method includes patterning a substrate to form trenches; etching the substrate, thereby modifying the trenches with round tips; forming a stack including conductive layers and dielectric layers in the trenches, wherein the conductive layers and the dielectric layers alternate with one another within the stack; forming an insulating compressive film in the first trenches, thereby sealing voids in the trenches; and forming conductive plugs connected to the conductive layers, respectively.

Abstract: Systems and methods described herein relate, among other things, to unmixing more than three stains, while preserving the biological constraints of the biomarkers. Unlimited numbers of markers may be unmixed from a limited-channel image, such as an RGB image, without adding any mathematical complicity to the model. Known co-localization information of different biomarkers within the same tissue section enables defining fixed upper bounds for the number of stains at one pixel. A group sparsity model may be leveraged to explicitly model the fractions of stain contributions from the co-localized biomarkers into one group to yield a least squares solution within the group. A sparse solution may be obtained among the groups to ensure that only a small number of groups with a total number of stains being less than the upper bound are activated.

Abstract: A method of controlling cooling water treatment at a cooling tower may involve measuring operating data of one or more downstream heat exchangers that receive cooling water from the cooling tower. For example, the inlet and outlet temperatures of both the hot and cold streams of a downstream heat exchanger may be measured, optionally along with a flow rate of the cooling water stream passing through the heat exchanger. Data from the streams passing through the heat exchanger may be used to determine a heat transfer efficiency for the heat exchanger. The heat transfer efficiency can be trended over a period of time and changes in the trend detected to identify cooling water fouling issues. A chemical additive selected to reduce, eliminate, or otherwise control the cooling water fouling can be controlled based on the changes in heat transfer efficiency detected at the downstream heat exchanger.

Abstract: A multiband antenna includes a first radiator, a feed element, a first ground element, a second radiator, a connecting element, and a second ground element, wherein the first radiator is made of a metal plate. The feed element is electrically connected to the first radiator and is adapted to feed a signal. The first ground element is electrically connected to the first radiator. The second radiator is made of a metal plate and surrounds an outer side of the first radiator, wherein the first radiator and the second radiator are spaced by an interval. The connecting element is electrically connected to the first radiator and the second radiator. The second ground element is electrically connected to the second radiator. In this way, the multiband antenna is suitable for transmitting signals in multiple frequency bands.

Abstract: Some implementations described herein provide for techniques to form a biased backside deep trench isolation and grid structure for a backside illumination image sensor. The techniques include forming an array of backside deep trench isolation structures and a biasing-pad that electrically connects to the array of metal-filled backside deep trench isolation structures through the grid structure. The array of backside deep trench isolation structures, the grid structure, and the biasing-pad structure may reduce a likelihood of electrical cross-talk and/or oblique light cross-talk between the photodiodes of the backside illumination image sensor. In this way, a performance of the backside illumination image sensor may be improved. Such improvements may include a suppression of a dark current within the backside illumination image sensor, a reduction in a number of white pixels, and a reduction in cross-talk within the backside illumination image sensor.

Abstract: A conjugate cam reducer includes input and output units disposed at two opposite sides of a transmission unit. The transmission unit includes smaller-diameter and larger-diameter cam discs axially connected with each other. The smaller-diameter and larger-diameter cam discs have first and second grooves. The input unit includes an input disc, an eccentric shaft and a plurality of input rollers. The input disc has a smaller inner peripheral wall engaging with the smaller-diameter cam disc, and a plurality of first receiving grooves registered with the first grooves to receive the input rollers. The eccentric shaft is rotated to drive rotation of the transmission unit in an eccentric cycloidal motion. The output unit includes an output disc having a larger inner peripheral wall which engages with the larger-diameter cam disc, and a plurality of second receiving grooves which are registered with the second grooves to receive a plurality of output rollers.

Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.

Abstract: A quick coupling set includes a socket and a mating plug. The socket has a rotation-restraining structure while the mating plug has a mating rotation-restraining structure. In the coupling of the socket and the mating plug, the rotation-restraining structure of the socket only allow the rotation-restraining structure of the mating plug to relatively rotate in a rotation direction, so as to complete the coupling of the socket and the mating plug. Other plugs which do not match the socket lack of a rotation-restraining structure matching that of the socket, and cannot relatively rotate in the rotation direction with respect to the socket and cannot achieve any coupling with the socket, which results in the socket and the mating plug being protected against misconnection.

Abstract: A semiconductor device includes: first and second input circuits in a central region and correspondingly configured to operate in a first voltage domain; first and second single bit level shifters (SBLSs) correspondingly in first and second regions at first and second sides of the central region relative to a first direction and electrically coupled correspondingly to the first and second input circuits, and correspondingly configured to operate in a second voltage domain; and a control circuit configured to toggle each of the first and second SBLSs between a normal state and a standby state when a control signal is received from the control circuit.

Abstract: An electronic device includes a display surface, a back surface with a first portion and a second portion, and a support assembly. The support assembly includes a first, second, and third boards. The first board includes a first surface, detachably covering the first portion, and a second surface. The second board is bendably connected to the first board and combined with the second portion. The third board includes a pivoted end and a free end. The pivoted end is pivotally connected to the second surface and covers the second board and a portion of the first board. When the first board rotates relative to the first portion, the third board also rotates relative to the second board, the second surface faces the third board, and the second board simultaneously moves along the third board. Accordingly, the display surface is raised up a distance relative to the free end.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

Abstract: In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.

Abstract: The image recognition method includes: obtaining an image data stream, wherein the image data frame includes a current frame; performing image recognition on an object in the current frame to generate a first box corresponding to the current frame; detecting movement of the object to generate a second box corresponding to the current frame; and determining the object as a tracking target according to the first box and the second box.

Abstract: An electronic device includes a first body including a first part and a second part hinged to each other, a second body, and a hinge structure hinged between an edge of the second body and the second part. The first part has a recess. When the second body is unfolded relative to the first body from a folded state to a first unfolded state, the hinge structure pushes against the first part to rotate the first part relative to the second part. When the second body is continuously unfolded relative to the first body from the first unfolded state to a second unfolded state, the edge of the second body pushes against the first part, so that the first part continues to rotate relative to the second part. When the second body is in the folded state, the hinge structure is at least partially accommodated in the recess.

Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.