Patents by Inventor Ting Chu

Ting Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11257844
    Abstract: A semiconductor device includes a lower intermetal dielectric (IMD) layer, a middle conductive line, and a ferroelectric random access memory (FRAM) structure. The middle conductive line is embedded in the lower IMD layer. The FRAM structure is over the lower IMD layer and the middle conductive line. The FRAM structure includes a bottom electrode, a ferroelectric layer, and a top electrode. The bottom electrode is over the middle conductive line and in contact with the lower IMD layer. The ferroelectric layer is over the bottom electrode. The top electrode is over the ferroelectric layer.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Yu Chen, Sheng-Hung Shih, Kuo-Chi Tu, Wen-Ting Chu
  • Patent number: 11239279
    Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Chieh Yang, Hsia-Wei Chen, Chih-Yang Chang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 11227872
    Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsiang Chang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Tzu-Yu Chen, Fu-Chen Chang
  • Publication number: 20220013494
    Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 11222971
    Abstract: The present invention provides a silicon carbide (SiC) semiconductor device integrating a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bidirectional voltage clamping circuit. An object of protecting a device is achieved by using the simple structure above, effectively preventing device damage that may be caused by a positive overvoltage and a negative overvoltage between a gate and a source.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: January 11, 2022
    Assignee: Shanghai Hestia Power Inc.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Fu-Jen Hsu, Kuo-Ting Chu
  • Publication number: 20210408373
    Abstract: A method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; forming a buffer layer over the bottom electrode layer; performing a surface treatment to a top surface of the buffer layer; depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element below the top electrode.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsia-Wei CHEN, Chih-Hung PAN, Chih-Hsiang CHANG, Yu-Wen LIAO, Wen-Ting CHU
  • Patent number: 11201190
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 11201281
    Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
  • Publication number: 20210384421
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.
    Type: Application
    Filed: August 25, 2021
    Publication date: December 9, 2021
    Inventors: Chieh-Fei Chiu, Wen-Ting Chu, Yong-Shiuan Tsair, Yu-Wen Liao, Chin-Yu Mei, Po-Hao Tseng
  • Patent number: 11195840
    Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Yong-Shiuan Tsair
  • Patent number: 11189788
    Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu
  • Publication number: 20210366988
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 11183631
    Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a bottom electrode that is disposed over a lower interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A data storage structure is arranged over the bottom electrode and a multi-layer top electrode is disposed over the data storage structure. The multi-layer top electrode includes conductive top electrode layers separated by an oxygen barrier structure that is configured to mitigate movement of oxygen between the conductive top electrode layers. A sidewall spacer is disposed directly over the bottom electrode and has a sidewall that covers outermost sidewalls of the conductive top electrode layers and the oxygen barrier structure.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ting Chu, Tong-Chern Ong, Ying-Lang Wang
  • Patent number: 11184003
    Abstract: A silicon carbide power device is controlled by a driver and comprises a gate-to-source voltage and a source voltage, wherein the source voltage decreases according to an increase of the gate-to-source voltage, or the source voltage increases according to a decrease of the gate-to-source voltage. Thus, a spike caused by a change of the gate-to-source voltage is suppressed, thereby suppressing the crosstalk phenomenon of the silicon carbide power device.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: November 23, 2021
    Assignee: SHANGHAI HESTIA POWER INC.
    Inventors: Fu-Jen Hsu, Chien-Chung Hung, Kuo-Ting Chu, Chwan-Ying Lee
  • Patent number: 11183503
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Chih-Hsiang Chang, Fu-Chen Chang
  • Publication number: 20210351126
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 11169605
    Abstract: An operating method in a virtual environment through a wearable device is disclosed, wherein the wearable device has a motion sensor, the virtual environment has an operated object and a virtual device corresponding to the wearable device, the corresponding virtual device has a first operational data constraint, and the operated object has a second operational data constraint. The operating method comprises the following steps of: using the motion sensor to generate a motion sensed data; causing the corresponding virtual device to generate a derived data according to the motion sensed data, wherein the derived data indicates an interaction relationship between the virtual device and the operated object; and when the virtual device separated from the operated object under the interaction relationship, moving the operated object in accordance with the derived data.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: November 9, 2021
    Assignee: J-MEX INC.
    Inventors: Chin-Ting Chu, Chia-Wei Lee, Chih-Hung Hsu, Te-Hsi Chen, Chi-Hung Chen, Meng-Yu Lee
  • Publication number: 20210296401
    Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
    Type: Application
    Filed: June 9, 2021
    Publication date: September 23, 2021
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 11127708
    Abstract: Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Kai Liu, Han-Ping Pu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20210280245
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 9, 2021
    Inventors: Yu-Der CHIH, Chung-Cheng CHOU, Wen-Ting CHU