Abstract: A method for forming a semiconductor memory structure includes forming an MTJ stack over a substrate. The method also includes etching the MTJ stack to form an MTJ device. The method also includes depositing a metal layer over a top surface and sidewalls of the MTJ device. The method also includes oxidizing the metal layer to form an oxidized metal layer. The method also includes depositing a cap layer over the oxidized metal layer. The method also includes oxidizing the cap layer to form an oxidized cap layer. The method also includes removing an un-oxidized portion of the cap layer.

Abstract: Disclosed are methods for producing steviol glycosides, such as rebaudioside D and rebaudioside M, using engineered yeast. The methods include at least two phases: first and second phases where a glucose-containing feed composition is provided to the medium in different modes of feeding in each phase, such as variable feeding and then constant feeding. The two phase feeding can result in a growth rate that is slower in the second phase than in the first phase, and consequently increased steviol glycoside production rates, reduced fermentation times, and reduced biomass concentrations.

Abstract: Sweetener compositions comprising particular glycoside blends are described in this paper. The glycioside blends comprise rebaudioside A, rebaudioside B, and/or rebaudioside D in various proportions. The sweetener composition can also include one or more bulking agents or other ingredients. The sweetener compositions can be used in foods and beverages.

Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

Abstract: Methods and apparatus for a magnetoresistive (MR) sensor including a seed layer having a CoFe layer for canceling hysteresis in the MR sensor. The MR stackup can include a free layer and a reference layer. The seed layer having CoFe provides a desired texturing of the stackup to cancel hysteresis effects.

Abstract: A calibration device for an intraoral scanner is provided. The calibration device includes a base, a moving portion, a circuit board, and a sensor. The moving portion is disposed on the base. The moving portion is moveable on the base along an extending direction of the calibration device. The moving portion includes a driving structure, a position determining portion, and a target plate. The position determining portion is coupled to and driven by the driving structure. The position determining portion has a first feature portion and a second feature portion different from the first feature portion. The target plate is coupled to the position determining portion. The circuit board is disposed at one side of the moving portion. The sensor is disposed on the circuit board. The sensor is configured to detect the first feature portion and the second feature portion to determine a position of the moving portion.

Abstract: In one aspect, a method includes forming a coil in a coil layer, performing planarization on the coil layer, and depositing a magnetoresistance (MR) element on the planarized coil layer. No dielectric material is between the planarized coil layer and the MR element. In another aspect, a magnetic field sensor includes a substrate, a planarized coil layer comprising a coil on the substrate, a magnetoresistance (MR) element in contact with the planarized coil layer, and a capping layer deposited over the MR element and the planarized coil layer. No dielectric material is between the planarized coil layer and the MR element.

Abstract: The present disclosure provides an electronic device including a substrate, an extending element, a conductive element and a first insulating layer. The substrate includes an edge. The extending element is disposed on the substrate and includes a first conductive layer and a semiconductor layer, the first conductive layer and the semiconductor layer are overlapped, and the semiconductor layer extends to the edge of the substrate. The conductive element is overlapped with the first conductive layer. The insulating layer is disposed between the conductive element and the extending element.

Abstract: A virtual reality system with an inspecting function of assembling and disassembling and an inspection method of assembling and disassembling based on virtual reality are presented. A learning-end acquires an inspection data and a teaching assembling-disassembling record being set with a plurality of checkpoints, plays the teaching assembling-disassembling record, modifies a learning assembling-disassembling status of a plurality of virtual objects based on user's operations for assembling or disassembling. The learning-end issues an assembling-disassembling error reminder when the learning assembling-disassembling status is inconsistent with a teaching assembling-disassembling status at any of the checkpoints.

Abstract: A rotation mechanism, includes a middle housing (1), a first support (2) and a second support (3), a first end of the first support is rotatably connected to the middle housing, and a second end of the first support is fixedly connected to a first housing; a first end of the second support is rotatably connected to the middle housing, and a second end of the second support is fixedly connected to a second housing.

Abstract: A speed generation method for simulating riding is provided. A computer device (20) retrieves a riding weight and road condition information, selects one of a plurality of preset gear ratios (30) as a selected gear ratio, retrieves a wheel rotating speed of a bicycle (4), and determines a simulated speed in a simulating riding service based on the selected gear ratio, a tire parameter, and the rotating speed.

Abstract: The present disclosure provides an electronic device including a substrate, a conductive pad, a chip and an insulating layer. The conductive pad is disposed on the substrate. The chip is disposed on the conductive pad. The insulating layer is disposed between the conductive pad and the chip, wherein the insulating layer includes an opening, and the chip is electrically connected to the conductive pad through the opening. An outline of the opening includes a plurality of curved corners in a normal direction of the substrate.

Abstract: A receiving circuit of a deserializer is provided. The receiving circuit of the deserializer receives an input signal and includes: a signal receiving terminal for receiving the input signal; a link equalizer circuit (LEQ) having a first input terminal coupled to the signal receiving terminal; and an out-of-band signaling (OOBS) circuit having a second input terminal coupled to the signal receiving terminal; a first resistor coupled between the signal receiving terminal and a first reference voltage; and a second resistor coupled between the signal receiving terminal and a second reference voltage; and a buffer circuit having a third input terminal and an output terminal, wherein the third input terminal receives a voltage, and the output terminal is coupled to the LEQ or the OOBS circuit. The first input terminal of the LEQ and the second input terminal of the OOBS circuit are not electrically coupled, and the voltage is adjustable.

Abstract: Systems and methods for a weakly supervised action localization model are provided. Example models according to example aspects of the present disclosure can localize and/or classify actions in untrimmed videos using machine-learned models, such as convolutional neural networks. The example models can predict temporal intervals of human actions given video-level class labels with no requirement of temporal localization information of actions. The example models can recognize actions and identify a sparse set of keyframes associated with actions through adaptive temporal pooling of video frames, wherein the loss function of the model is composed of a classification error and a sparsity of frame selection. Following action recognition with sparse keyframe attention, temporal proposals for action can be extracted using temporal class activation mappings, and final time intervals can be estimated corresponding to target actions.

Abstract: Provided is a use of a Neurog2 functional fragment. The functional fragment can induce, in vivo or in vitro, glial cell formation into functional neuron cells, and thus can not only have a transdifferentiation function in normal tissue, but also facilitate neural reconstruction of damaged neural tissue.

Abstract: An electronic device interfaced with a multiple digital signatures security engine, internally or externally, which enable the device to obtain PUF-based security credentials with the option to generate multiple unique digital signatures from the same source of PUF entropy. The multiple digital signatures security zone includes a source of PUF entropy dynamically measurable, a non-volatile memory storage media and a digital circuitry performing all the functions requested by the electronic device interfaced. The electronic device is able to select and switch between which unique digital signature to be involved for its related cybersecurity applications without depending on power-up sequences or single time operations after power-up sequence.

Abstract: A management device comprises a first authentication module, for receiving a first information and performing a first determination on whether an administrator device is correct according to the first information; an authorization module, coupled to the first authentication module, for performing a second determination on whether the administrator device comprises an access qualification for a remote device, when the first determination is positive and when receiving a first request message for accessing the remote device; a communication module, coupled to the authorization module, for transmitting a second request message for establishing a connection with a network device to the remote device, when the second determination is positive and when determining to establish the connection with the network device; an integration module, coupled to the authorization module, for transmitting a third request message for configuring a port forwarding to the network device, when the second determination is positive.

Abstract: A packing method for a defective sheet based on branch-and-cut algorithm, including: acquiring sheet information, where the sheet information includes size information of the defect sheet, size information of a target block and position information of a defect; based on actual cutting requirements, establishing constraints; and establishing a primal problem model according to the constraints; converting the primal problem model into a relaxed problem model; checking and verifying the obtained solution by x-check method to determine whether the obtained solution meets the constraints of the primal problem model; outputting the optimal solution to obtain an optimal cutting plan that meets the actual cutting requirements; and cutting the defective sheet according to the optimal cutting plan. A system for implement the packing method is also provided.

Abstract: A semiconductor layer structure may include a substrate, a blocking layer disposed over the substrate, and one or more epitaxial layers disposed over the blocking layer. The blocking layer may have a thickness of between 50 nanometers (nm) and 4000 nm. The blocking layer may be configured to suppress defects from the substrate propagating to the one or more epitaxial layers. The one or more epitaxial layers may include a quantum-well layer that includes a quantum-well intermixing region formed using a high temperature treatment.