Abstract: The application relates to a method for manufacturing an electronic device, and in particular, to a method for manufacturing an electronic device with a carrier substrate. The method includes: providing a carrier; forming a first base layer on the carrier; and forming working units on the first base layer. The working units are spaced apart from one another.

Abstract: A rotating mechanism includes a main shaft assembly, a first fastening bracket, a first transmission arm, a first rotation arm, a first support plate, a second fastening bracket, a second transmission arm, a second rotation arm, and a second support plate. One end of the first transmission arm is slidably connected to the first fastening bracket, and the other end is rotatably connected to the main shaft assembly. Two ends of the first rotation arm are rotatably connected to the first fastening bracket and the main shaft assembly respectively.

Abstract: Methods and apparatus for a sensor including a series of tunneling magnetoresistance (TMR) pillars and a heatsink adjacent to at least one of the TMR pillars, where the heatsink comprises Titanium Nitride (TiN).

Abstract: The present disclosure is directed to an in situ closed-loop radio frequency (RF) power management on RF processes such as a plasma etch process, a plasma chemical vapor deposition process, a plasma physical vapor deposition process, a plasma clean process, or the like. An RF power measurement device according to one or more embodiments of the present disclosure assists the in situ closed-loop RF power management on RF processes. In some embodiments, the RF power measurement device includes a coil-shaped current sensor that is wound around the path between an RF generator and a chamber. The coil-shaped current sensor senses the current flowing through this path so that the power of the RF generator may be calibrated without having to separate the RF generator for separate analysis and calibration. The RF power measurement device allows management of RF power in an in situ closed-loop manner.

Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

Abstract: A cryogenic system cools and operates cryogenic electronics. The cryogenic system includes a cryogenic stage or multiple cryogenic stages for cooling the cryogenic electronics to an operational cryogenic temperature. The cryogenic stage or stages transfer heat from the cryogenic electronics to an ambient environment. An optical fiber or multiple optical fibers deliver an operational power from the ambient environment to the cryogenic electronics and transfer communication data between the cryogenic electronics and the ambient environment. Preferably, the only connection delivering any power from the ambient environment to the cryogenic electronics or transferring any data from the cryogenic electronics to the ambient environment is the optical fiber or fibers, such that the cryogenic system does not include any electrically conductive wires spanning between the ambient environment and the cryogenic electronics.

Abstract: A fan casing for mounting of a fan includes a frame including four corner segments and four side segments that are arranged alternately with the corner segments, a seat disposed in the frame, and four support members extending radially and outwardly from the seat and connected respectively to the corner segments. Each support member includes a base connected to the seat and having a width reducing in a direction away from the seat, and a rib connected between the base and the corresponding corner segment. The bases are interconnected to surround the seat. Any two adjacent bases are interconnected to form an arc surface facing the corresponding side segment and adapted to absorb shock.

Abstract: The present invention provides a QFN packaging structure and QFN packaging method. By providing the insulating layer on the outer side of the leads of the QFN packaging structure, a short circuit between the leads and the electromagnetic shielding layer can be prevented. In addition, the grounding lead is exposed from the insulating layer, such that the electromagnetic shielding layer is grounded via the grounding lead, thereby realizing the electromagnetic shielding design of the QFN packaging structure.

Abstract: The present invention provides a QFN packaging structure and QFN packaging method. The electromagnetic shielding layer as provided on the outer side of the QFN packaging structure by spacing at a certain interval from the leads may cooperate with the base island having the lug boss on the side edge, such that all surfaces of the chip can be electromagnetically shielded and protected while ensuring the insulation between the electromagnetic shielding layer and the leads.

Abstract: A display device includes a pixel array substrate and a circuit board. The pixel array substrate has a first surface, a second surface opposite to the first surface, and a first side surface connecting the first surface and the second surface. Multiple bonding pads are located on the first surface. The circuit board is bent from above the first surface of the pixel array substrate to below the second surface. The circuit board is electrically connected to the bonding pads and includes a thermoplastic substrate. The thermoplastic substrate includes a third surface facing the pixel array substrate and a fourth surface opposite to the third surface. The thermoplastic substrate includes a first bend formed by thermoplastics.

Abstract: A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer including a first dielectric layer, a conductive layer, and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test mark, the test mark includes a plurality of conductive patterns formed of the conductive layer, and the conductive patterns are arranged in a ring shape.

Abstract: This disclosure relates to an apparatus and methods for applying X-ray reflectometry (XRR) in characterizing three dimensional nanostructures supported on a flat substrate with a miniscule sampling area and a thickness in nanometers. In particular, this disclosure is targeted for addressing the difficulties encountered when XRR is applied to samples with intricate nanostructures along all three directions, e.g. arrays of nanostructured poles or shafts. Convergent X-ray with long wavelength, greater than that from a copper anode of 0.154 nm and less than twice of the characteristic dimensions along the film thickness direction, is preferably used with appropriate collimations on both incident and detection arms to enable the XRR for measurements of samples with limited sample area and scattering volumes.

Abstract: Novel steviol glycoside compounds characterized by a first group of four glucopyranose residues attached via the number 13 carbon (C13) of the steviol moiety and a second group of two or three glucopyranose residues attached via the number 19 carbon (C19) of the steviol moiety are described, and exemplified by compounds 1-4. These compounds can be present in a composition with other steviol glycosides (e.g., Reb D and Reb M) to enhance their solubilities. Accordingly, the novel compounds can facilitate the preparation of aqueous compositions having a higher concentration of steviol glycosides. A steviol glycoside composition including one or more of compounds 1-4 can be used as a sweetener composition to sweeten other compositions (sweetenable compositions) such as foods, beverages, medicines, oral hygiene compositions, nutraceuticals, and the like.

Abstract: An airtight device includes a container and an airtight cover on the container, and the airtight cover includes a fixing bracket, a door, and a pressuring handle. The fixing bracket has a through hole and a guiding slot, and the through hole communicates with internal space of the container. The guiding slot has adjacent first and second top surfaces, and the second top surface is higher than the first top surface. The door selectively covers the through hole. The pressuring handle pivoted on the door has a first section, a second section, and a rotating axis between the first and second sections, and the first section rotates relative to the second section. The second section receives a force to drive the first section to move from below the second top surface to below the first top surface such that the rotating axis pressures the door.

Abstract: The present invention relates to a layered semi-parallel LDPC decoder system having a single permutation network, and belongs to the field of decoder hardware design. The system comprises a layered decoding architecture of the single permutation network, a layered semi-parallel decoding architecture of the single permutation network, a pipeline design for layered semi-parallel decoding and a hardware framework of a layered semi-parallel LDPC decoder. The present invention removes a permutation network module between a check node and a variable node by modifying the cyclic shift value of each information block transferred from the variable node to the check node, i.e., the cyclic shift operation of the decoder can be completed through the single permutation network so as to reduce hardware resources of the decoder. A semi-parallel decoding structure is adopted, and meanwhile, a pipeline is added between half layers.

Abstract: The present invention discloses a method for determining a maximum value of a heart activity parameter of a user performing a physical activity. Acquire first heart activity data in a first duration of the physical activity performed by the user. Acquire motion data in the first duration of the physical activity performed by the user. Calculate second heart activity data based on the motion data in the first duration of the physical activity performed by the user by a mathematical model and estimate the maximum value of the heart activity parameter of the user based on a comparison between the first heart activity data and the second heart activity data.

Abstract: A semiconductor device includes an active region. A metal gate electrode is disposed over the active region. A conductive layer is disposed over the metal gate electrode. A silicon-containing layer is disposed over a first portion of the conductive layer. A dielectric layer is disposed over a second portion of the conductive layer. A gate via vertically extends through the silicon-containing layer. The gate via is disposed over, and electrically coupled to, the metal gate electrode.

Abstract: The embodiments of the present disclosure provide a cell culture composition and a use thereof, and the cell culture composition includes a culture medium and mitochondria. The cell culture composition including mitochondria can promote cell growth and improve the function of the damaged or aged stem cells, thereby improving overall cell growth.

Abstract: An immersion cooling system includes a tank, a first condenser, an enclosure, a second condenser and a connecting pipe. The tank has a first space. The first space is configured to accommodate a cooling liquid for at least one electronic equipment to immerse therein. The first condenser is disposed inside the tank. The enclosure is disposed outside the tank. The enclosure forms a second space together with the tank. The second condenser is disposed in the second space. The connecting pipe includes a first end and a second end opposite to the first end. The first end is connected with the second condenser. The second end is communicated with the first space.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.