Patents by Inventor Ting Wu

Ting Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11802891
    Abstract: Embodiments are directed to probe structures, arrays, methods of using probes and arrays, and/or methods for making probes and/or arrays. In the various embodiments, probes include at least two flat spring segments with at least one of those segments being used in a compressive manner wherein the probe additionally includes guide elements, framing structures or other structural configurations that limit or inhibit one or more compressive spring segments from bowing or deflecting out of a desired position when subjected to loading.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: October 31, 2023
    Assignee: Microfabrica Inc.
    Inventor: Ming Ting Wu
  • Patent number: 11805615
    Abstract: A method of manufacturing a casing of an electronic device including the following steps is provided. A metallic housing is provided, wherein the metallic housing has an inner surface and an outer surface opposite to the inner surface and includes a back region and at least one side region. At least one gap, a plurality of apertures and a non-conductive layer are formed on the inner surface of the metallic housing, wherein the apertures is formed on a surface of the at least one gap, part of the non-conductive layer is formed in the at least one gap and extended from the back region to the at least one side region, and part of the non-conductive layer is extended into the apertures. Part of the metallic housing is removed for exposing part of the non-conductive layer, thereby forming a plurality of non-conductive spacers located in the at least one gap.
    Type: Grant
    Filed: July 17, 2022
    Date of Patent: October 31, 2023
    Assignee: HTC Corporation
    Inventors: Tim Chung-Ting Wu, Cheng-Chieh Chuang, Chi-Jen Lu, Chun-Lung Chu, Chien-Hung Lin
  • Publication number: 20230340457
    Abstract: The technology described herein is directed to compositions, sets, and methods for analyzing, detecting, and/or visualizing target molecules. In one aspect, described herein are sets of readout molecules to determine the identity of at least one oligonucleotide tag hybridized to at least one target molecule. In another aspect, described herein are methods of detecting said oligonucleotide tags bound to at least one target molecules using said set of readout molecules.
    Type: Application
    Filed: November 24, 2020
    Publication date: October 26, 2023
    Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Huy Quoc NGUYEN, Shyamtanu CHATTORAJ, Chao-ting WU
  • Publication number: 20230343379
    Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
    Type: Application
    Filed: May 16, 2022
    Publication date: October 26, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
  • Patent number: 11793435
    Abstract: The present disclosure provides a method for detecting the focus of attention. The method includes: obtaining the face of a person in the first image, as well as the result of facial recognition; determining whether the distance between the person and the target is within an effective attention range; determining whether the face is frontal; determining whether the effective attention period is not shorter than a period threshold; detecting the focus of attention for the person to the target.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: October 24, 2023
    Assignee: ACER INCORPORATED
    Inventors: Kuan-Chung Hou, Bo-Ting Wu, Chian-Ying Li, Ming-Hsuan Tu, Chien-Hung Lin, Jian-Chi Lin, Fu-Heng Wu, Kai-Lun Chang, Tsung-Yao Chen
  • Patent number: 11789548
    Abstract: An input mouse may include a top button, a first wall rearward of the top button to underlie a palm of a user and a second wall forming an exterior of the input mouse. The first wall is formed from a material composition comprising a first polymer encapsulating thermally conductive particles. The second wall is formed from a thermally conductive material. A solid-state Peltier heat pump has a first face thermally coupled to the first wall and a second face thermally coupled to the second wall.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 17, 2023
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hsiao-Jou Lin, Kuan-Ting Wu, Alexander Williams
  • Publication number: 20230324435
    Abstract: Pin probes and pin probe arrays are provided that allow electric contact to be made with selected electronic circuit components. Some embodiments include one or more compliant pin elements located within a sheath. Some embodiments include pin probes that include locking or latching elements that may be used to fix pin portions of probes into sheaths. Some embodiments provide for fabrication of probes using multi-layer electrochemical fabrication methods.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 12, 2023
    Applicant: Microfabrica Inc.
    Inventors: Arun S. Veeramani, Ming Ting Wu, Uri Frodis, Heath A. Jensen
  • Publication number: 20230326805
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20230324436
    Abstract: Some embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes for use in die level testing of semiconductor devices) from a core material and a shell or coating material that partially coats the surface of the structure. Other embodiments are directed to electrochemical fabrication methods for producing structures or devices (e.g. microprobes) from a core material and a shell or coating material that completely coats the surface of each layer from which the probe is formed including interlayer regions. Additional embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes) from a core material and a shell or coating material wherein the coating material is located around each layer of the structure without locating the coating material in inter-layer regions.
    Type: Application
    Filed: March 21, 2023
    Publication date: October 12, 2023
    Applicant: University of Southern California
    Inventors: Ming Ting Wu, Rulon J. Larsen, III, Young Kim, Kieun Kim, Adam L. Cohen, Ananda H. Kumar, Michael S. Lockard, Dennis R. Smalley
  • Publication number: 20230326806
    Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, a first isolation structure on the SDB structure, a shallow trench isolation (STI) adjacent to the SDB structure, and a second isolation structure on the STI. Preferably, the first isolation structure further includes a cap layer on the SDB structure and a dielectric layer on the cap layer.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20230314482
    Abstract: Probe array for contacting electronic components includes a plurality of probes for making contact between two electronic circuit elements and a dual array plate mounting and retention configuration. The probes may comprise one or more mounting features that extend laterally from a body portion of the probe and the lower and upper array plates, in combination, capture: (1) at least one of the mounting features to inhibit excessive downward vertical movement of the probe body relative to the array plates, (2) at least one of the mounting features to inhibit excessive upward vertical movement of the probe body relative to the array plates, and (3) at least one of the mounting features to inhibit excessive lateral movement of the probe relative to the array plates, and wherein the at least one lower and upper plates longitudinally contact each other in a stacked assembly.
    Type: Application
    Filed: April 4, 2023
    Publication date: October 5, 2023
    Inventors: Arun S. Veeramani, Ming Ting Wu, Dennis R. Smalley
  • Publication number: 20230314474
    Abstract: A method of forming a probe, comprises providing a first and a second probe modules, having respective compliant element functionally joining respective probes arm that directly or indirectly holds a first and a second tips and forming the probe by laterally and longitudinally aligning the first and second probe modules with their respective tips pointing away from each other.
    Type: Application
    Filed: April 4, 2023
    Publication date: October 5, 2023
    Inventors: Arun S. Veeramani, Ming Ting Wu, Dennis R. Smalley
  • Patent number: 11777957
    Abstract: Disclosed is a method for detection a malicious attack based on deep learning in a transportation cyber-physical system (TCPS), comprising: extracting original feature data of a malicious data flow and a normal data flow from a TCPS; cleaning and coding original feature data; selecting key features from the feature data; cleaning and coding the key features to establish a deep learning model; finally, inputing unknown behavior data to be identified into the deep learning model to identify whether the data is malicious data, thereby detecting a malicious attack. The present invention uses a deep learning method to extract and learn the behavior of a program in a TCPS, and detect the malicious attack according to the deep learning result, and effectively identify the malicious attack in the TCPS.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 3, 2023
    Assignee: HANGZHOU DIANZI UNIVERSITY
    Inventors: Yuanfang Chen, Ting Wu, Hengli Yue, Chengnan Hu
  • Patent number: 11775017
    Abstract: The present disclosure is drawn to bendable displays for electronic devices. In one example, a first display region including a glass panel that is rigid, the glass panel including a first interlocking edge. A second display region can include a plastic panel that is bendable, the plastic panel including a second interlocking edge that is shaped to inversely correspond with the first interlocking edge. An interlock zone where the first interlocking edge can be joined with the second interlocking edge such that the first display region and the second display region form a continuous display panel that is bendable at a location along the second display region.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: October 3, 2023
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Super Liao, Kuan-Ting Wu, Hsing-Hung Hsieh
  • Publication number: 20230307292
    Abstract: An integrated circuit (IC) structure includes a substrate, an interconnect structure, metal lines, a liner, a protecting layer, and a nitride-free passivation layer. The interconnect structure is over the substrate. The metal lines are over the interconnect structure. The liner is conformally formed on the metal lines. The protecting layer is over the liner. The nitride-free passivation layer continuously extends from the liner to the protecting layer and forms an interface with the liner.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 28, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chiang CHEN, Chun-Ting WU, Ching-Hou SU, Chih-Pin WANG
  • Patent number: 11768227
    Abstract: Embodiments are directed to probes formed from multiple layers with at least a portion of the layers including portions that include elastic compliant regions of the probes wherein such elastic portions of different layers are formed of different materials and wherein a plane of preferred elastic deformation of the probes is parallel to a plane containing (1) a normal to the planes of the layers and (2) a longitudinal axes of the probes or a local longitudinal axes of the probes.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: September 26, 2023
    Assignee: MICROFABRICA INC.
    Inventor: Ming Ting Wu
  • Publication number: 20230298995
    Abstract: A fusible structure includes: a metal line in a first metal layer extending along a first direction; and a first dummy structure disposed proximal to the metal line relative to a second direction, the second direction being perpendicular to the first direction, the first dummy structure being in a second metal layer. Relative to the first direction, the metal line includes first, second and third portions, the second portion being between the first portion and third portion. Relative to a third direction that is perpendicular to the first direction and the second direction, the first portion has a first thickness and the second portion has a second thickness, the first thickness being greater than the second thickness.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 21, 2023
    Inventors: Shao-Ting WU, Meng-Sheng CHANG, Shao-Yu CHOU, Chung-I HUANG
  • Publication number: 20230298516
    Abstract: A display having an area of non-transparent pixels, an area of transparent pixels, a camera positioned behind the transparent pixels to capture an image when light passes through the transparent pixels, and a display controller for driving the non-transparent pixels at a first brightness and driving the transparent pixels at a second brightness greater than the first brightness during image capture by the camera.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Hsing-Hung Hsieh, Kuan-Ting Wu, Dehuei Chen
  • Patent number: 11762427
    Abstract: The present disclosure is drawn to covers for electronic devices. In one example, a cover for an electronic device can include an aluminum or aluminum alloy cover frame having an opening. A magnesium or magnesium alloy cover panel supported by the aluminum or aluminum alloy cover frame within or over the opening. A protective coating can be over a surface of the aluminum or aluminum alloy cover frame and a surface of the magnesium or magnesium alloy cover panel. A chamfered edge can include a chamfer at an edge of the aluminum or aluminum alloy cover frame. The chamfer can expose the aluminum or aluminum alloy cover frame beneath the protective coating, and the chamfer at the same time does not expose the magnesium or magnesium alloy cover panel.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: September 19, 2023
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kuan-Ting Wu, Ya-Ting Yeh, Chih-Hsiung Liao
  • Patent number: 11757440
    Abstract: A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the control terminal of the first transistor and the output terminal of the inverter circuit.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: September 12, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Yen-Ting Wu