Patents by Inventor TING YEH

TING YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170076
    Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.
    Type: Application
    Filed: November 17, 2022
    Publication date: May 23, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue, Tzu-Hsuan Hsu, Chen-Huan Chen, Ken-Hui Chen
  • Publication number: 20240170046
    Abstract: A memory device, such as three dimension AND Flash memory, including a plurality of word line decoding circuit areas, a plurality of common power rails and a plurality of power drivers is provided. The word line decoding circuit areas are arranged in an array, and form a plurality of isolation areas, wherein each of the isolation areas is disposed between two adjacent word line decoding circuit areas. Each of the common power rails is disposed along the isolation areas. The power drivers respectively correspond to the word line decoding circuit areas. Each of the power drivers is disposed between each of the power driving circuit areas and each of the corresponding isolation areas, wherein each of the power drivers is configured to provide a common power to the word line decoding circuit areas.
    Type: Application
    Filed: November 17, 2022
    Publication date: May 23, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue, Chih-Wei Hu
  • Patent number: 11990351
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Publication number: 20240158943
    Abstract: The present disclosure is drawn to covers for electronic devices. In one example, a substrate can include a metal alloy. An acid anodizing layer can be formed on the substrate. A dye application can be applied on the acid anodizing layer. A first nickel-free sealing layer can be formed on the dye application. An alkaline anodizing layer can be formed on the first sealing layer. A second nickel-free sealing layer can be formed on the alkaline anodizing layer.
    Type: Application
    Filed: March 19, 2021
    Publication date: May 16, 2024
    Inventors: Qingyong GUO, Ya-Ting YEH, Chi Hao CHANG, Kuan-Ting WU
  • Publication number: 20240162401
    Abstract: A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.
    Type: Application
    Filed: December 9, 2022
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chun-Ting Yeh
  • Publication number: 20240162088
    Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsia-Wei CHEN, Fu-Ting SUNG, Yu-Wen LIAO, Wen-Ting CHU, Fa-Shen JIANG, Tzu-Hsuan YEH
  • Patent number: 11985822
    Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: May 14, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Chih-Wei Hu, Hang-Ting Lue, Guan-Ru Lee
  • Publication number: 20240153824
    Abstract: A method includes forming a stack of channel layers and sacrificial layers over a substrate, patterning the stack to form a fin-shape structure, and recessing a portion of the fin-shape structure to form a recess. A top surface of the substrate under the recess is covered at least by a bottommost sacrificial layer of the stack. The method also includes forming inner spacers on terminal ends of the sacrificial layers that are above the bottommost sacrificial layer, depositing an undoped layer in the recess, and forming a doped epitaxial feature over the undoped layer. The undoped layer covers terminal ends of a bottommost channel layer of the stack. The doped epitaxial feature covers terminal ends of the channel layers that are above the bottommost channel layer.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Ting-Yeh CHEN, Wei-Yang LEE, Po-Cheng WANG, De-Fang CHEN, Chao-Cheng CHEN
  • Publication number: 20240154447
    Abstract: A power system including a first battery pack, a second battery pack, and a power management circuit is disclosed. The first battery pack has a first end and a second end, and has a first battery capacity. The second battery pack has a third end and a fourth end. The third end is coupled to the second end of the first battery pack and provides a low battery voltage. The fourth end is grounded, the second battery pack has a second battery capacity, and the second battery capacity is greater than the first battery capacity. The power management circuit is coupled to the second battery pack to receive the low battery voltage, and provides a component operating voltage to an electronic components based on the low battery voltage.
    Type: Application
    Filed: August 29, 2023
    Publication date: May 9, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Yi-Hsuan Lee, Liang-Cheng Kuo, Chun-Wei Ko, Ya Ju Cheng, Chih Wei Huang, Ywh Woei Yeh, Yu Cheng Lin, Yen Ting Wang
  • Patent number: 11969518
    Abstract: The present invention provides an artificial dressing and a use of the artificial dressing for promoting wound healing. The artificial dressing includes a gelatin and a fungal extract.
    Type: Grant
    Filed: August 3, 2022
    Date of Patent: April 30, 2024
    Assignee: A.M.S. BioteQ Co., Ltd.
    Inventors: Yi-Ju Tsai, Ying-Ting Yeh, Meng-Yi Bai, Yun-Xuan Zhang
  • Patent number: 11971609
    Abstract: A photographing optical system includes eight lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element and an eighth lens element. The eight lens elements each have an object-side surface facing toward the object side and an image-side surface facing toward the image side. The first lens element has positive refractive power. The fifth lens element has positive refractive power. The object-side surface of the seventh lens element is convex in a paraxial region thereof. The image-side surface of the eighth lens element is concave in a paraxial region thereof. At least one lens surface of at least one lens element of the photographing optical system has at least one critical point in an off-axis region thereof.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: April 30, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Chun-Yen Chen, Kuan-Ting Yeh, Tzu-Chieh Kuo
  • Publication number: 20240136183
    Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Yu-Shih Wang, Hong-Jie Yang, Chia-Ying Lee, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11966031
    Abstract: An image lens assembly includes, in order from an object side to an image side along an optical path, a first lens group, a second lens group, a third lens group and a fourth lens group. A total number of lens elements in the image lens assembly is seven. The first lens group includes a first lens element with positive refractive power and a second lens element with negative refractive power. Each of the second lens group and the third lens group includes at least one lens element. The fourth lens group includes a seventh lens element. When the image lens assembly is focusing or zooming, a relative position between the first lens group and an image surface is fixed, a relative position between the fourth lens group and the image surface is fixed, and the second lens group and the third lens group move along the optical axis.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: April 23, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ting Yeh, Wei-Yu Chen
  • Publication number: 20240126045
    Abstract: An imaging system lens assembly includes, in order from an object side to an image side: a first lens element, a second lens element, a third lens element and a fourth lens element. Each of the four lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The second lens element has positive refractive power. The object-side surface of the third lens element is convex in a paraxial region thereof.
    Type: Application
    Filed: November 25, 2022
    Publication date: April 18, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ting YEH, Cheng-Yu TSAI
  • Publication number: 20240127955
    Abstract: Systems and methods for mapping cancer classification labels are provided. In a method for generating a cancer label for a cancer patient, the method entails acquiring, from a data source, a cancer classification for a cancer in the cancer patient; extracting, from the cancer classification, primary anatomic site, primary histology, and invasiveness (or behavior) of the cancer; identifying, in a lookup table, an entry having the extracted anatomic site, histology, and invasiveness (or behavior); and retrieving a corresponding cancer label in the entry for the cancer.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 18, 2024
    Inventors: Zhao Dong, Kathryn Nelson Kurtzman, Joerg Bredno, Xiaoji Chen, Amber Yeh, Ting Ma
  • Patent number: 11961796
    Abstract: A package comprises at least one first device die, and a redistribution line (RDL) structure having the at least one first device die bonded thereto. The RDL structure comprises a plurality of dielectric layers, and a plurality of RDLs formed through the plurality of dielectric layers. A trench is defined proximate to axial edges of the RDL structure through each of the plurality of dielectric layers. The trench prevents damage to portions of the RDL structure located axially inwards of the trench.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yueh-Ting Lin, Hua-Wei Tseng, Ming Shih Yeh, Der-Chyang Yeh
  • Publication number: 20240118522
    Abstract: A photographing lens assembly includes, in order from an object side to an image side: a first, a second, a third, a fourth, a fifth and a sixth lens elements. The first lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof, wherein the object-side surface has at least one convex critical point in an off-axis region thereof. The third lens element has an image-side surface being convex in a paraxial region thereof. The fourth lens element has positive refractive power. The fifth lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof, and an image-side surface being convex in a paraxial region thereof. The sixth lens element has an image-side surface being concave in a paraxial region thereof, wherein the image-side surface has at least one convex critical point in an off-axis region thereof.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 11, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Po-Lun HSU, Wei-Yu CHEN, Kuan-Ting YEH, Ssu-Hsin LIU
  • Patent number: 11948896
    Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure, wherein the first stacked die package structure comprises a plurality of memory dies. The underfill layer is over the first stacked die package structure. the package layer is over the underfill layer, wherein the package layer has a protruding portion that extends below a top surface of the through substrate via structure.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
  • Patent number: 11943935
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Patent number: 11940597
    Abstract: An image capturing optical lens system includes four lens elements, which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element and a fourth lens element. The first lens element has an object-side surface being convex in a paraxial region thereof. The third lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The fourth lens element has negative refractive power.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: March 26, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ting Yeh, Wei-Yu Chen