Patents by Inventor Ting Yen
Ting Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085634Abstract: An optical fiber transmission device includes a substrate, a photonic integrated circuit, and an optical fiber assembly. The photonic integrated circuit is disposed on an area of the substrate. The substrate has a protruding structure at an interface with an edge of the photonic integrated circuit. The optical fiber assembly includes an optical fiber and a ferrule that sleeves the optical fiber. The protruding structure of the substrate is configured to abut against the ferrule to limit the position of the optical fiber assembly in a vertical direction of the substrate, such that the protruding structure is a stopper for the optical fiber assembly in the vertical direction.Type: ApplicationFiled: September 14, 2023Publication date: March 14, 2024Applicant: AuthenX Inc.Inventors: Chun-Chiang YEN, Po-Kuan SHEN, Sheng-Fu LIN, Yi-Ting LU, Jun-Rong CHEN, Jenq-Yang CHANG, Mao-Jen WU
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Publication number: 20240077540Abstract: An electronic device includes a battery device, a capacity measuring unit, and a microprocessor. The battery device outputs its remaining capacity and fully charged capacity. The capacity measuring unit includes a sensing resistor, measures the battery current of the battery device using the sensing resistor, and integrates the battery current to obtain the actual capacity. The microprocessor stores the fully charged capacity. When the battery device is in a specific state, the microprocessor calculates the capacity difference between the remaining capacity and the actual capacity. The microprocessor calibrates the fully charged capacity according to the ratio of the capacity difference to the remaining capacity.Type: ApplicationFiled: November 18, 2022Publication date: March 7, 2024Inventor: Wei-Ting YEN
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Patent number: 11923243Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.Type: GrantFiled: August 30, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yen Huang, Ting-Ya Lo, Shao-Kuan Lee, Chi-Lin Teng, Cheng-Chin Lee, Shau-Lin Shue, Hsiao-Kang Chang
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Publication number: 20240069618Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: ApplicationFiled: April 27, 2023Publication date: February 29, 2024Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
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Patent number: 11915936Abstract: A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.Type: GrantFiled: January 11, 2023Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Wei Su, Fu-Ting Yen, Ting-Ting Chen, Teng-Chun Tsai
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Patent number: 11908921Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.Type: GrantFiled: August 26, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Yun Peng, Fu-Ting Yen, Keng-Chu Lin
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Patent number: 11855213Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.Type: GrantFiled: April 4, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Hao Yeh, Fu-Ting Yen
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Patent number: 11855214Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.Type: GrantFiled: March 15, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.Inventors: Yu-Yun Peng, Fu-Ting Yen, Ting-Ting Chen, Keng-Chu Lin, Tsu-Hsiu Perng
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Publication number: 20230395683Abstract: A post-deposition treatment can be applied to an atomic layer deposition (ALD)-deposited film to seal one or more seams at the surface. The seam-top treatment can physically merge the two sides of the seam, so that the surface behaves as a continuous material to allow etching at a substantially uniform rate across the surface of the film. The seam-top treatment can be used to merge seams in ALD-deposited films within semiconductor structures, such as gate-all-around field effect transistors (GAAFETs).Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuei-Lin CHAN, Fu-Ting YEN, Yu-Yun PENG, Keng-Chu LIN
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Publication number: 20230387065Abstract: The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: De-Yang CHIOU, Yu-Yun Peng, Fu-Ting Yen, Keng-Chu Lin
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Patent number: 11801585Abstract: A pliers includes a first pliers body (10) and a second pliers body (20). The first pliers body includes a first handle (11) and a first clamp (12). A first pliers knife (13) and a first pliers back (14) are disposed on the first clamp (12). The second pliers body (20) includes a second handle (21) and a second clamp (22). A second pliers knife (23) and a second pliers back (24) are disposed on the second clamp (22). The second clamp (22) is pivotally connected with the first clamp (12) to clamp or cut. The first pliers back (14) or the second pliers back (24) is provided with a chipping blade (50) configured in a concave arc shape for chipping.Type: GrantFiled: July 15, 2021Date of Patent: October 31, 2023Assignee: KAUW YEHI INDUSTRIAL CO., LTD.Inventor: Yu-Ting Yen
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Publication number: 20230326988Abstract: A device includes at least one semiconductor unit which includes a first source/drain portion, a second source/drain portion, at least one nanosheet segment which is disposed to interconnect the first and second source/drain portions, a gate portion disposed around the at least one nanosheet segment, and a first inner spacer portion and a second inner spacer portion which are disposed to separate the gate portion from the first and second source/drain portions, respectively. Each of the first and second inner spacer portions has a carbon-rich region which confronts the gate portion.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Ting YEN, Kuei-Lin CHAN, Yu-Yun PENG
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Publication number: 20230307938Abstract: A charging system for a smart battery, including a control device, is provided. The control device includes a processing circuit, configured to receive the charging voltage parameter and the charging current parameter, which were configured by the user, from the bus, and to cause the charging circuit to charge the battery according to the charging voltage parameter and the charging current parameter.Type: ApplicationFiled: April 12, 2022Publication date: September 28, 2023Inventor: Wei-Ting YEN
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Publication number: 20230268268Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.Type: ApplicationFiled: April 24, 2023Publication date: August 24, 2023Inventors: KHADERBAD MRUNAL ABHIJITH, YU-YUN PENG, FU-TING YEN, CHEN-HAN WANG, TSU-HSIU PERNG, KENG-CHU LIN
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Publication number: 20230253240Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
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Patent number: 11664268Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.Type: GrantFiled: July 12, 2021Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
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Publication number: 20230146366Abstract: A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.Type: ApplicationFiled: January 11, 2023Publication date: May 11, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Wei SU, Fu-Ting YEN, Ting-Ting CHEN, Teng-Chun TSAI
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Publication number: 20230147804Abstract: An optical path correction subassembly, an optical detection assembly, and an optical detection system are provided. The optical path correction subassembly can be optionally configured to be applied to a light detector. The optical path correction subassembly includes a holder structure and an optical path correction structure carried by the holder structure, and the optical path correction structure has a light beam guiding surface arranged as a reverse inclination inclined relative to a vertical line. The light beam guiding surface of the optical path correction structure can be configured to effectively or accurately guide a predetermined light beam to a light receiving surface of the light detector so as to facilitate collection of the predetermined light beam. The light beam guiding surface of the optical path correction structure can be arranged at an acute angle relative to the light receiving surface of the light detector.Type: ApplicationFiled: November 2, 2022Publication date: May 11, 2023Inventors: PO-YI TING, TING-AN YEN, YU-HSUN HSU, SEBASTIAN GIESSMANN
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Publication number: 20230141093Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.Type: ApplicationFiled: January 2, 2023Publication date: May 11, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Yu LIN, Jhih-Rong HUANG, Yen-Tien TUNG, Tzer-Min SHEN, Fu-Ting YEN, Gary CHAN, Keng-Chu LIN, Li-Te LIN, Pinyen LIN
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Patent number: 11637062Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.Type: GrantFiled: February 21, 2022Date of Patent: April 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Khaderbad Mrunal Abhijith, Yu-Yun Peng, Fu-Ting Yen, Chen-Han Wang, Tsu-Hsiu Perng, Keng-Chu Lin