Abstract: A battery device with a C-rate of 1 C includes a battery cell, a protection chip, and a microcontroller. The protection chip is electrically connected to the battery cell, determines whether to activate the protection mechanism of the battery device according to the state of the battery cell. The microcontroller is electrically connected to the protection chip, detects the RSOC of the battery cell. When an external power supply is electrically coupled to the battery device, and the RSOC of the battery cell is lower than 50%, the microcontroller controls the battery cell to perform a fast charging not over 10 minutes. During the 10 minutes of fast charging, the protection chip activates the protection mechanism, or the microcontroller detects that the battery cell has changed from a CC state to a CV state, the microcontroller stops the fast charging and restores the C-rate of the battery cell to 1 C.

Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.

Abstract: A switch chip includes a first switch device, a first ESD protection device and a second ESD protection device. The first switch device is electrically coupled between a first pad and a second pad. The first ESD protection device is electrically coupled to a third pad which is electrically coupled to the first pad by a first bond wire. The second ESD protection device is electrically coupled to a fourth pad which is electrically coupled to the second pad by a second bond wire.

Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.

Abstract: The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.

Abstract: A Quality of Experience (QoE) optimization system and method are provided. An electronic device inputs key performance indicators (KPIs) and system control parameters collected from a core network, a base station and a user equipment (UE) into a QoE optimization model. The QoE optimization model then optimizes the system control parameters based on the KPIs and a user QoE fed back from the UE to output optimized system control parameters. Furthermore, a strategy emulator controls at least one of a base station emulator and a UE emulator, so as to emulate the QoE optimization model using the at least one of the base station emulator and the UE emulator. Non-real-time optimization adjustments to the QoE optimization model are made based on the result of the emulation performed by the at least one of the base station emulator and the UE emulator.

Abstract: A battery device includes a battery cell and a battery protection circuit. The battery protection circuit includes a microcontroller and a power-supply switch. The microcontroller receives a start signal, a repair signal, and an external-power-indication signal from the outside of the battery device. The power-supply switch is electrically connected to the battery cell. The microcontroller correspondingly outputs an enable signal to the power-supply switch according to the start signal and the repair signal, so that the power-supply switch disconnects the electrical connection between the battery cell and the battery protection circuit. The microcontroller correspondingly outputs a disable signal to the power-supply switch according to the start signal, the repair signal, and the external-power-indication signal, so that the power-supply switch restores the electrical connection between the battery cell and the battery protection circuit.

Abstract: A pliers includes a first pliers body (10) and a second pliers body (20). The first pliers body includes a first handle (11) and a first clamp (12). A first pliers knife (13) and a first pliers back (14) are disposed on the first clamp (12). The second pliers body (20) includes a second handle (21) and a second clamp (22). A second pliers knife (23) and a second pliers back (24) are disposed on the second clamp (22). The second clamp (22) is pivotally connected with the first clamp (12) to clamp or cut. The first pliers back (14) or the second pliers back (24) is provided with a chipping blade (50) configured in a concave arc shape for chipping.

Abstract: A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.

Abstract: A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a source/drain (S/D) opening in the superlattice structure, forming an isolation opening in the fin structure and below the S/D opening, forming a first isolation layer in the isolation opening, selectively forming an oxide layer on sidewalls of the S/D opening, selectively forming an inhibitor layer on the oxide layer, selectively depositing a second isolation layer on the first isolation layer, and forming S/D regions in the S/D opening on the second isolation layer.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.

Abstract: A method for fault diagnosis in a communication network is to be implemented by a processor. The method includes obtaining key performance indicator (KPI) data related to the communication network, performing a deep-learning-based classification algorithm by using the KPI data as input to a deep neural network model, and determining, based on output of the deep neural network model after performing the deep-learning-based classification algorithm, at least one type of network condition the communication network currently satisfies, and a severity level of the at least one type of network condition when the output of the deep neural network model contains information related to severity levels of the at least one type of network condition.

Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; performing a plasma treatment to a first portion of the dielectric layer, such that a carbon concentration of the first portion of the dielectric layer is lower than a carbon concentration of a second portion of the dielectric layer; selectively forming an inhibitor over the first portion of the dielectric layer; and selectively forming a hard mask over portions of the metal layer that is uncovered by the inhibitor.

Abstract: A signal control module integrated to a low coherence interferometry including a one-dimensional (1D) array image sensor is provided. The signal control module includes an image acquisition controller and a signal controller. The image acquisition controller sends a 1D image acquisition control signal. The signal controller sends a two-dimensional (2D) image acquisition control signal, wherein the 1D and 2D image acquisition control signals are synchronized with each other. The 1D array image sensor captures 1D image information of an object-to-be-tested at different positions along a direction according to the 1D and 2D image acquisition control signals. The 1D image information constitutes 2D image information. Furthermore, a low coherence interferometry is provided.

Abstract: The disclosure provides a method for interacting with a virtual environment, an electronic device, and a computer readable storage medium. The method includes: displaying a virtual environment, wherein the virtual environment includes a virtual object and a controller representative object having a first visual type; defining a detection space, wherein the virtual object locates in the detection space; in response to determining that the controller representative object locates in the detection space or a gaze direction of a user of the electronic device points to the detection space, transforming the controller representative object to a second visual type, wherein the controller representative object with the second visual type is used to interact with the virtual object; and adjusting the virtual environment in response to determining that the controller representative object with the second visual type reaches the virtual object.

Abstract: A Quality of Experience (QoE) optimization system and method are provided. An electronic device inputs key performance indicators (KPIs) and system control parameters collected from a core network, a base station and a user equipment (UE) into a QoE optimization model. The QoE optimization model then optimizes the system control parameters based on the KPIs and a user QoE fed back from the UE to output optimized system control parameters. Furthermore, a strategy emulator controls at least one of a base station emulator and a UE emulator, so as to emulate the QoE optimization model using the at least one of the base station emulator and the UE emulator. Non-real-time optimization adjustments to the QoE optimization model are made based on the result of the emulation performed by the at least one of the base station emulator and the UE emulator.

Abstract: A smart battery device includes a battery unit, a temperature-sensing unit and a processing unit. The temperature-sensing unit senses the ambient temperature to generate a temperature signal. The processing unit is coupled to the battery unit and the temperature-sensing unit. In a charging mode, the processing unit receives the temperature signal and obtains the power capacity of the battery unit. The processing unit sets full capacity according to the temperature signal and generates an indication flag when the power capacity of the battery unit reaches the full capacity, wherein the indication flag is used to indicate that the battery unit is in a fully charged state.

Abstract: The battery device includes an energy storage unit, a temperature sensing unit, a storage unit, and a processing unit. The processing unit calculates the internal resistance of the energy storage unit to obtain a first increment corresponding to the internal resistance, and detects the charging voltage that is charging the battery device to obtain a second increment that corresponds to the charging voltage. The processing unit detects the discharging current of the energy storage unit to obtain a third increment corresponding to the discharging current. The processing unit further reads the cycle count from the storage unit to obtain a fourth increment that corresponds to the cycle count, reads the temperature from the temperature sensing unit to obtain a fifth increment that corresponds to the temperature, and determines the swelling rate of the battery device according to the product value of the first, second, third, fourth, and fifth increments.

Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.