Abstract: Embodiments herein describe dummy gates disposed over a portion of a fin in finFETs. That is, instead of separating the dummy gates from the finFET structure, the fins may be extended and covered, at least partially, by the dummy gates. An insulative material is disposed between the dummy gate and the fin in order to form a decoupling capacitor. In one embodiment, the dummy gate overlaps a portion of the fin that is held at a voltage rail. Moreover, the dummy gate may be coupled to a different (e.g., opposite) voltage rail than rail coupled to the fin. For example, if the fin is coupled to VHIGH then the dummy gate is coupled to VLOW, or vice versa. Thus, the capacitor formed using the fin and the dummy gate provides a decoupling capacitance between the power sources generating the voltage rails (i.e., VHIGH and VLOW).

Abstract: Embodiments herein describe dummy gates disposed over a portion of a fin in finFETs. That is, instead of separating the dummy gates from the finFET structure, the fins may be extended and covered, at least partially, by the dummy gates. An insulative material is disposed between the dummy gate and the fin in order to form a decoupling capacitor. In one embodiment, the dummy gate overlaps a portion of the fin that is held at a voltage rail. Moreover, the dummy gate may be coupled to a different (e.g., opposite) voltage rail than rail coupled to the fin. For example, if the fin is coupled to VHIGH then the dummy gate is coupled to VLOW, or vice versa. Thus, the capacitor formed using the fin and the dummy gate provides a decoupling capacitance between the power sources generating the voltage rails (i.e., VHIGH and VLOW).

Abstract: A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuity having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination.

Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.

Abstract: A capacitor can be fabricated within an integrated circuit (IC) by creating, in a top surface of a dielectric layer of the IC, a recess having at least one side and a bottom, the bottom adjacent to a first conductive structure. A first plate of the capacitor may be formed by depositing a conductive liner onto the at least one side and the bottom of the recess. A conformal dielectric film may be deposited onto the first plate within the recess, and a second plate of the capacitor may be formed by filling a portion of the recess that is not filled by the conformal dielectric film with an electrically conductive material that is electrically insulated, by the conformal dielectric film, from the first plate.

Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.

Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.

Abstract: A utility tower/pole monitoring system having a plurality of monitoring devices mounted to a plurality of utility tower/poles. The monitoring devices include an accelerometer, gyroscope, and a GPS device. The monitoring devices transmit acceleratory and positional data to a data aggregation system for processing and storage. The data aggregation system displays status data on a map on a website that is easily accessible and downloadable by an end user such as a lineman.

Abstract: A capacitor can be fabricated within an integrated circuit (IC) by creating, in a top surface of a dielectric layer of the IC, a recess having at least one side and a bottom, the bottom adjacent to a first conductive structure. A first plate of the capacitor may be formed by depositing a conductive liner onto the at least one side and the bottom of the recess. A conformal dielectric film may be deposited onto the first plate within the recess, and a second plate of the capacitor may be formed by filling a portion of the recess that is not filled by the conformal dielectric film with an electrically conductive material that is electrically insulated, by the conformal dielectric film, from the first plate.

Abstract: Embodiments herein describe a decoupling capacitor that may include multiple fin and gate structures electrically insulated from a conductor (e.g., a metal layer) by a thin dielectric. The fins and gates may be electrically coupled to a first voltage rail (e.g., VHIGH) while the conductor is coupled to a second voltage rail (e.g., VLOW). In this manner, the fins and gates in combination form a first “plate” which is electrically insulated from the conductor which forms a second “plate” of a capacitor. In one embodiment, the decoupling capacitor is formed on the same substrate as the finFETs, and thus, can be disposed proximate to the finFETs—e.g., on the same layer in the chip or side-by-side. In one example, at least a portion of the decoupling capacitor and the finFET may be formed using the same fabrication steps.

Abstract: A method and circuit for implementing enhanced performance dynamic evaluation, and a design structure on which the subject circuit resides are provided. The dynamic evaluation circuit includes a combined precharge and keeper device connected to a precharge node. The dynamic evaluation circuit includes control logic providing a control input to the combined precharge and keeper device. The combined precharge and keeper device responsive to the control input holds the precharge node precharged when the precharge node is not discharged early in an evaluate cycle.

Abstract: A method and circuit for implementing enhanced performance dynamic evaluation, and a design structure on which the subject circuit resides are provided. The dynamic evaluation circuit includes a combined precharge and keeper device connected to a precharge node. The dynamic evaluation circuit includes control logic providing a control input to the combined precharge and keeper device. The combined precharge and keeper device responsive to the control input holds the precharge node precharged when the precharge node is not discharged early in an evaluate cycle.

Abstract: A method and circuit for implementing enhanced performance dynamic evaluation, and a design structure on which the subject circuit resides are provided. The dynamic evaluation circuit includes a combined precharge and keeper device connected to a precharge node. The dynamic evaluation circuit includes control logic providing a control input to the combined precharge and keeper device. The combined precharge and keeper device responsive to the control input holds the precharge node precharged when the precharge node is not discharged early in an evaluate cycle.

Abstract: A method and circuit for implementing enhanced performance dynamic evaluation, and a design structure on which the subject circuit resides are provided. The dynamic evaluation circuit includes a combined precharge and keeper device connected to a precharge node. The dynamic evaluation circuit includes control logic providing a control input to the combined precharge and keeper device. The combined precharge and keeper device responsive to the control input holds the precharge node precharged when the precharge node is not discharged early in an evaluate cycle.

Abstract: A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit.

Abstract: A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit.

Abstract: A TCAM may have a plurality of rows of cells. Each row may have a match line. Each cell may have elements for storing first and second bits, and compare circuitry associated to determine matches between a bit of a search word and data stored in the cell. For at least one first row of the rows, the TCAM includes a valid row cell having at least one element to store a partial update indication. The valid row cell may cause the match line associated with the first row to signal that the first row does not match a search word when the partial update indication associated with the first row is enabled. When the partial update indication associated with the first row is disabled, the determination of matches with a search word is performed solely by the compare circuitry without influence of the valid row cell.

Abstract: A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit.

Abstract: A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit.

Abstract: A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region.