Patents by Inventor Tokumasa Hara

Tokumasa Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11100999
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: August 24, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • Publication number: 20210166755
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Application
    Filed: January 21, 2021
    Publication date: June 3, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Tokumasa HARA, Noboru SHIBATA
  • Publication number: 20210158867
    Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.
    Type: Application
    Filed: September 10, 2020
    Publication date: May 27, 2021
    Applicant: Kioxia Corporation
    Inventors: Tokumasa HARA, Noboru SHIBATA
  • Publication number: 20210118495
    Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tokumasa HARA
  • Publication number: 20210082497
    Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventors: Tokumasa HARA, Noboru SHIBATA
  • Publication number: 20210082524
    Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
    Type: Application
    Filed: November 25, 2020
    Publication date: March 18, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki AKAMINE, Masanobu SHIRAKAWA, Tokumasa HARA
  • Publication number: 20210074363
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Hiroshi SUKEGAWA, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • Patent number: 10937490
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: March 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Patent number: 10916300
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit is received from an external controller, the received first data is written to the first memory cell. When second data including a second bit and a third bit is received from the controller after the first data is received, the first bit is read from the first memory cell and the 3-bit data is written to the first memory cell based on the read first bit and the received second data. In the 3-bit data written to the first memory cell, lower bit data is determined by three read operations, middle bit data is determined by two read operations, and upper bit data is determined by two read operations.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: February 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tokumasa Hara
  • Patent number: 10885988
    Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: January 5, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Akamine, Masanobu Shirakawa, Tokumasa Hara
  • Patent number: 10878913
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • Patent number: 10871901
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: December 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • Publication number: 20200335158
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Tokumasa HARA, Noboru Shibata
  • Patent number: 10790017
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: September 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Publication number: 20200302999
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit is received from an external controller, the received first data is written to the first memory cell. When second data including a second bit and a third bit is received from the controller after the first data is received, the first bit is read from the first memory cell and the 3-bit data is written to the first memory cell based on the read first bit and the received second data. In the 3-bit data written to the first memory cell, lower bit data is determined by three read operations, middle bit data is determined by two read operations, and upper bit data is determined by two read operations.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tokumasa HARA
  • Publication number: 20200285418
    Abstract: According to an embodiment, a memory system is connectable to a host. The memory system includes a memory controller and a memory chip. The memory chip includes a processing circuit and a first storage area including a plurality of word lines. The memory controller is configured to cause the processing circuit to execute a first access to the first storage area. The memory controller is configured to transmit a first command to the memory chip after completion of the first access. The memory controller is configured to transmit a second command to the memory chip before causing the processing circuit to execute a second access subsequent to the first access. The processing circuit is configured to start applying a first voltage to the word lines in response to the first command, and end applying the first voltage to the word lines in response to the second command.
    Type: Application
    Filed: August 28, 2019
    Publication date: September 10, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Tokumasa HARA
  • Publication number: 20200285388
    Abstract: A memory device includes memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Masanobu SHIRAKAWA, Tokumasa HARA
  • Patent number: 10719395
    Abstract: According to one embodiment, a memory system includes an error mitigation encoder that executes error mitigation coding on write data to be stored in a processing target page of a non-volatile memory, a memory interface that writes the write data which has undergone the error mitigation coding in the processing target page of the non-volatile memory and reads the write data which has undergone the error mitigation coding from the processing target page as read data, an error mitigation decoder that performs error mitigation decoding on the read data read from the processing target page of the non-volatile memory, and an error mitigation coding rate deciding unit that decides an error mitigation coding rate of the error mitigation encoder and the error mitigation decoder on the basis of at least one of information indicating the processing target page and information indicating a device characteristic of the processing target page.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: July 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Kejen Lin, Sho Kodama, Keiri Nakanishi, Kohei Oikawa
  • Patent number: 10714170
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit is received from an external controller, the received first data is written to the first memory cell. When second data including a second bit and a third bit is received from the controller after the first data is received, the first bit is read from the first memory cell and the 3-bit data is written to the first memory cell based on the read first bit and the received second data. In the 3-bit data written to the first memory cell, lower bit data is determined by three read operations, middle bit data is determined by two read operations, and upper bit data is determined by two read operations.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: July 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tokumasa Hara
  • Patent number: 10698611
    Abstract: A memory device includes memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 30, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masanobu Shirakawa, Tokumasa Hara