Patents by Inventor Tokumasa Hara

Tokumasa Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system, memory controller and memory control method
    Patent number: 9927990
    Abstract: According to an embodiment, a memory system includes: a non-volatile memory; an encoding unit that generates a code word in which zero and one occur at different occurrence rates by encoding data; and a control unit that writes k third data items and fourth data items into the non-volatile memory. The k is an integer larger than or equal to zero and smaller than or equal to n. The n is an integer larger than or equal to two. The k third data items are obtained by encoding k second data items with the encoding unit among first data items including n second data items and having a first data length. The fourth data items are obtained by removing data corresponding to the k third data items from the first data items. The third data items are generated by encoding the second data items with encoders, respectively.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Osamu Torii, Tokumasa Hara, Hironori Uchikawa
  • Memory controller, storage device, and read retry method
    Patent number: 9928920
    Abstract: According to one embodiment, a temperature of a non-volatile memory or an ambient temperature of the non-volatile memory is acquired. A distribution of a threshold voltage, which is corrected according to the acquired temperature, is acquired from the non-volatile memory. Read voltages related to the reading of data are detected from the distribution. Error correction is performed for data read from the non-volatile memory, using the read voltages. The detected read voltages are separately corrected on the basis of the acquired temperature when the error correction has failed.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiko Kurosawa, Tsuyoshi Atsumi, Masanobu Shirakawa, Tokumasa Hara, Naoya Tokiwa
  • MEMORY SYSTEM
    Publication number: 20180068719
    Abstract: According to one embodiment, a controller writes first processed data acquired by a first process into a nonvolatile memory during a first period. The controller writes second processed data acquired by a second process into the nonvolatile memory during a second period. The first process is for the purpose of improving the endurance of memory cells. The second process is for the purpose of decreasing inter-cell interferences between adjacent cells.
    Type: Application
    Filed: March 15, 2017
    Publication date: March 8, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Kejen LIN, Tokumasa HARA, Hironori UCHIKAWA, Juan SHI, Akira YAMAGA, Sho KODAMA, Keiri NAKANISHI
  • Memory system and method for controlling nonvolatile memory
    Patent number: 9891848
    Abstract: According to one embodiment, a nonvolatile memory system includes a memory including a first memory and a second memory, the first memory including memory strings, the memory strings including memory cell transistors connected in series; and a memory controller which compresses a failure string position information of the first memory, which stores the compressed failure string position information in the second memory, and which decompresses the compressed failure string position information stored in the second memory.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shohei Asami, Tokumasa Hara, Hiroshi Yao, Kenichiro Yoshii, Riki Suzuki, Toshikatsu Hida, Osamu Torii
  • Memory system
    Patent number: 9891837
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: February 13, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • Memory system and method of controlling nonvolatile memory by converting write data written to a page
    Patent number: 9865338
    Abstract: A controller executes a first data conversion for write data to be written into a first page. The first data conversion includes increasing a ratio of a number of a first value to a total number of pieces of data. The controller executes a second data conversion for write data to be written into a second page. The second data conversion includes increasing a ratio of the number of the second value to the total number of pieces of data.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tokumasa Hara, Kiichi Tachi, Susumu Tamon, Shigefumi Irieda
  • Memory device and method of reading data
    Patent number: 9847135
    Abstract: A memory device of an embodiment includes a memory cell array and a controller. In the memory cell, data is written per page unit and is erased per block which is a multiple the page unit of a natural number of two or more. The block includes memory strings, each including memory cells capable of storing data of one or more bits with a threshold voltage indicative of an erase state in which data is erased and one or more threshold voltages which are higher than the voltage indicative of the erase state and indicate written states in which data is written. The controller selects one of adjustment values of positive and negative values based on data read from a first memory cell of the memory cells, and reads data from a second memory cell of the memory cells using the selected adjustment value and a first read voltage.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: December 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tokumasa Hara, Hitoshi Iwai
  • Memory system and writing method
    Patent number: 9830983
    Abstract: A nonvolatile memory device includes memory cells, bit lines, a word line, and a control unit performing a write operation in first and second stages. During the first stage, the control unit applies voltages to the word line and the bit lines based on first page of data to maintain threshold voltages for a first group of memory cells and shift the threshold voltages for a second group of memory cells above a first threshold. During the second stage, the control unit applies voltages to the word line and the bit lines based on second and third pages of data to shift the threshold voltages of memory cells in the first group to threshold voltages in one of first, second, and third threshold voltage ranges and the threshold voltages of memory cells in the second group to threshold voltages in one of fourth, fifth, sixth, and seventh threshold voltage ranges.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: November 28, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Memory device cable of high write efficency
    Patent number: 9817598
    Abstract: A memory device includes a first memory string including a first selection transistor and a first memory cell, a second memory string including a second selection transistor and a second memory cell, a bit line electrically connected to the first memory string and the second memory string, and a control circuit configured to perform a collective write operation on the first memory cell and the second memory cell by applying a voltage to turn on the first transistor, a voltage to turn on the second transistor, and then a program voltage at the same time to gates of the first and second memory cells.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: November 14, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Hidehiro Shiga, Masanobu Shirakawa, Tokumasa Hara
  • Memory system
    Patent number: 9799406
    Abstract: A memory system includes a memory device, and a controller which controls the memory device. The memory device includes a plurality of memory cells capable of rewriting data, a plurality of word lines connected to the plurality of memory cells, a page including the plurality of memory cells connected to the same word line, a plane including a plurality of pages, a memory cell array including a plurality of planes, and a plurality of word line drivers which apply voltages to the plurality of word lines, and a plurality of switches provided for each plane and which assigns the word line drivers to the word lines.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: October 24, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Manabu Sato, Daiki Watanabe, Hiroshi Sukegawa, Tokumasa Hara, Hiroshi Yao, Naomi Takeda, Noboru Shibata, Takahiro Shimizu
  • MEMORY SYSTEM
    Publication number: 20170262379
    Abstract: According to one embodiment, a controller writes either processed data or preprocessing data and flags into each page included in m pages. The processed data is data after first data translation of write data to be written into a relevant page. The preprocessing data is data before the first data translation of the write data to be written into the relevant page. Each of the flag at least represents whether or not the first data translation is performed for write data to be written into the relevant page.
    Type: Application
    Filed: September 12, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tokumasa HARA, Osamu Torii, Kiichi Tachi, Susumu Tamon, Shigefumi Irieda, Juan Shi, Hironori Uchikawa, Kejen Lin, Akira Yamaga
  • MEMORY SYSTEM
    Publication number: 20170263331
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that performs programming and reading out with respect to the non-volatile memory, a code processor that generates a code word by encoding; and a controller that sets a threshold-voltage read level for determining whether a value of each bit in a received word read out from the non-volatile memory is “0” or “1”. A difference between the number of bits which have value equals “0” and the number of bits which have value equals “1” in the code word depends on a code rate of the encoding. The controller obtains the threshold-voltage read level based on the code rate.
    Type: Application
    Filed: March 14, 2016
    Publication date: September 14, 2017
    Inventors: Juan Shi, Hironori Uchikawa, Tokumasa Hara, Osamu Torii
  • Memory system
    Patent number: 9761325
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that performs programming and reading out with respect to the non -volatile memory, a code processor that generates a code word by encoding; and a controller that sets a threshold -voltage read level for determining whether a value of each bit in a received word read out from the non-volatile memory is “0” or “1”. A difference between the number of bits which have value equals “0” and the number of bits which have value equals “1” in the code word depends on a code rate of the encoding. The controller obtains the threshold-voltage read level based on the code rate.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: September 12, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Juan Shi, Hironori Uchikawa, Tokumasa Hara, Osamu Torii
  • MEMORY DEVICE CABLE OF HIGH WRITE EFFICENCY
    Publication number: 20170255410
    Abstract: A memory device includes a first memory string including a first selection transistor and a first memory cell, a second memory string including a second selection transistor and a second memory cell, a bit line electrically connected to the first memory string and the second memory string, and a control circuit configured to perform a collective write operation on the first memory cell and the second memory cell by applying a voltage to turn on the first transistor, a voltage to turn on the second transistor, and then a program voltage at the same time to gates of the first and second memory cells.
    Type: Application
    Filed: November 8, 2016
    Publication date: September 7, 2017
    Inventors: Hidehiro SHIGA, Masanobu SHIRAKAWA, Tokumasa HARA
  • MEMORY SYSTEM
    Publication number: 20170221569
    Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
    Type: Application
    Filed: March 10, 2016
    Publication date: August 3, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki AKAMINE, Masanobu SHIRAKAWA, Tokumasa HARA
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20170212703
    Abstract: According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.
    Type: Application
    Filed: April 7, 2017
    Publication date: July 27, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Riki Suzuki, Toshikatsu Hida, Tokumasa Hara
  • SEMICONDUCTOR MEMORY DEVICE INCLUDING STRINGS INCLUDING MEMORY CELL TRANSISTORS
    Publication number: 20170199705
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Application
    Filed: August 8, 2016
    Publication date: July 13, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi SUKEGAWA, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • Memory system and method of controlling nonvolatile memory
    Patent number: 9652167
    Abstract: According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: May 16, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Riki Suzuki, Toshikatsu Hida, Tokumasa Hara
  • MEMORY CONTROLLER, STORAGE DEVICE, AND READ RETRY METHOD
    Publication number: 20170076810
    Abstract: According to one embodiment, a temperature of a non-volatile memory or an ambient temperature of the non-volatile memory is acquired. A distribution of a threshold voltage, which is corrected according to the acquired temperature, is acquired from the non-volatile memory. Read voltages related to the reading of data are detected from the distribution. Error correction is performed for data read from the non-volatile memory, using the read voltages. The detected read voltages are separately corrected on the basis of the acquired temperature when the error correction has failed.
    Type: Application
    Filed: December 21, 2015
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko KUROSAWA, Tsuyoshi ATSUMI, Masanobu SHIRAKAWA, Tokumasa HARA, Naoya TOKIWA
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20170075604
    Abstract: According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.
    Type: Application
    Filed: October 18, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Riki SUZUKI, Toshikatsu Hida, Tokumasa Hara