Patents by Inventor Tokumasa Hara

Tokumasa Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NONVOLATILE MEMORY AND WRITING METHOD
    Publication number: 20190189201
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 20, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tokumasa HARA, Noboru SHIBATA
  • Memory system
    Patent number: 10289480
    Abstract: A memory system includes a memory and a controller. The memory includes a first memory chip and a second memory chip. The controller controls the memory. Each of the first and second memory chips includes string units and blocks including the string units. The memory holds information indicating a partial bad block including a bad string unit, and indicating which one of string units is the bad string unit in the partial bad block.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: May 14, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Naomi Takeda, Tokumasa Hara, Masanobu Shirakawa, Hiroshi Yao
  • MEMORY SYSTEM
    Publication number: 20190107947
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 11, 2019
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • Nonvolatile memory and writing method
    Patent number: 10255971
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tokumasa Hara, Noboru Shibata
  • SEMICONDUCTOR MEMORY DEVICE INCLUDING A CONTROL CIRCUIT AND AT LEAST TWO MEMORY CELL ARRAYS
    Publication number: 20190034081
    Abstract: A memory device includes memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Inventors: Masanobu SHIRAKAWA, Tokumasa Hara
  • Memory controller and semiconductor memory device
    Patent number: 10180876
    Abstract: A memory controller includes: a host interface configured to receive a read command from the outside of the memory controller; and a read controller configured to perform a data read operation on a memory device according to the read command. The read controller performs a data read operation on a set of memory cells and determines a first and second values. The first value is a number of memory cells having a first threshold voltage among the set of memory cells, and the second value is a number of memory cells having a second threshold voltage among the set of memory cells. The read controller determines a first read voltage based on only the first and second values and performs a data read operation on the set of memory cells using the first read voltage.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: January 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tokumasa Hara
  • Memory system utilizing a page buffer for prioritizing a subsequent read request over a pending write
    Patent number: 10180795
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • MEMORY SYSTEM
    Publication number: 20180358100
    Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
    Type: Application
    Filed: August 20, 2018
    Publication date: December 13, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki AKAMINE, Masanobu Shirakawa, Tokumasa Hara
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20180330792
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 15, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Hiroshi SUKEGAWA, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • Semiconductor memory device including a control circuit and at least two memory cell arrays
    Patent number: 10120584
    Abstract: A memory device includes memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: November 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Tokumasa Hara
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20180300071
    Abstract: According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.
    Type: Application
    Filed: June 19, 2018
    Publication date: October 18, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Riki SUZUKI, Toshikatsu HIDA, Tokumasa HARA
  • Memory system including multi-plane flash memory and controller
    Patent number: 10096366
    Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: October 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Akamine, Masanobu Shirakawa, Tokumasa Hara
  • Memory system
    Patent number: 10089241
    Abstract: According to one embodiment, a controller writes either processed data or preprocessing data and flags into each page included in m pages. The processed data is data after first data translation of write data to be written into a relevant page. The preprocessing data is data before the first data translation of the write data to be written into the relevant page. Each of the flag at least represents whether or not the first data translation is performed for write data to be written into the relevant page.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tokumasa Hara, Osamu Torii, Kiichi Tachi, Susumu Tamon, Shigefumi Irieda, Juan Shi, Hironori Uchikawa, Kejen Lin, Akira Yamaga
  • Write data optimization methods for non-volatile semiconductor memory devices
    Patent number: 10061691
    Abstract: According to one embodiment, a controller writes first processed data acquired by a first process into a nonvolatile memory during a first period. The controller writes second processed data acquired by a second process into the nonvolatile memory during a second period. The first process is for the purpose of improving the endurance of memory cells. The second process is for the purpose of decreasing inter-cell interferences between adjacent cells.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: August 28, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kejen Lin, Tokumasa Hara, Hironori Uchikawa, Juan Shi, Akira Yamaga, Sho Kodama, Keiri Nakanishi
  • 3D vertical NAND semiconductor memory device and methods thereof
    Patent number: 10062438
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 28, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    Publication number: 20180240515
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit and a second bit is received from an external controller, the received first data is written to the first memory cell. When second data including a third bit and a fourth bit is received after the first data is received from the controller, the first data is read from the first memory cell and the 3-bit data is written to the first memory cell based on 1-bit of the read first data and the received second data.
    Type: Application
    Filed: September 12, 2017
    Publication date: August 23, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tokumasa HARA
  • Memory system and method of controlling nonvolatile memory
    Patent number: 10025514
    Abstract: According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Riki Suzuki, Toshikatsu Hida, Tokumasa Hara
  • Memory system and method of controlling non-volatile memory
    Patent number: 9966146
    Abstract: According to one embodiment, a controller groups a plurality of memory cells in each of the pages into a plurality of groups. The plurality of groups includes a first group and a second group. In a case of reading data from a first page, The controller performs first reading. The first reading includes reading data from the first page by using a first operation parameter for the first group. The controller performs second reading. The second reading includes reading data from the first page by using a second operation parameter for the second group. The controller merges first read data and second read data, and return the merged data as read data read from the first page. The first read data is acquired by the first reading. The second read data is acquired by the second reading.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: May 8, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daiki Watanabe, Hiroshi Sukegawa, Hiroshi Yao, Tokumasa Hara, Naomi Takeda
  • MEMORY SYSTEM
    Publication number: 20180107389
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Application
    Filed: December 19, 2017
    Publication date: April 19, 2018
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • Semiconductor memory device that applies same voltage to two adjacent word lines for access
    Patent number: 9947408
    Abstract: A semiconductor memory device includes a block of memory cells including first, second, and third memory cells, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, a third word line electrically connected to a gate of the third memory cell, and a control circuit configured to access the block in one of at least first and second modes to perform an operation thereon. When the control circuit accesses the block in the first mode, the same voltage is applied to the first and second word lines throughout the operation, and when the control circuit accesses the block in the second mode, the same voltage is applied to the second and third word lines throughout the operation.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: April 17, 2018
    Assignee: Toshiba Memeory Corporation
    Inventors: Toshifumi Shano, Masanobu Shirakawa, Tokumasa Hara