Patents by Inventor Tokumasa Hara
Tokumasa Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220101915Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.Type: ApplicationFiled: December 8, 2021Publication date: March 31, 2022Applicant: Kioxia CorporationInventors: Tokumasa HARA, Noboru SHIBATA
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Patent number: 11289167Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.Type: GrantFiled: November 25, 2020Date of Patent: March 29, 2022Assignee: KIOXIA CORPORATIONInventors: Takayuki Akamine, Masanobu Shirakawa, Tokumasa Hara
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Publication number: 20220076772Abstract: According to one embodiment, a memory system includes a non-volatile memory provided with a plurality of memory cells, and a memory controller. The memory controller reads data subjected to error-mitigation encoding from the non-volatile memory, the data including determination information indicating whether or not a value is changed by the error-mitigation encoding, executes error-mitigation decoding on the read data, re-executes the error-mitigation encoding on a decoding result obtained by the error-mitigation decoding, and compares the determination information included in the read data with determination information included in data obtained by re-executing the error-mitigation encoding and outputs a comparison result.Type: ApplicationFiled: February 18, 2021Publication date: March 10, 2022Applicant: Kioxia CorporationInventors: Itaru HIDA, Tokumasa HARA
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Publication number: 20220075521Abstract: A memory system includes a memory device with a memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.Type: ApplicationFiled: November 16, 2021Publication date: March 10, 2022Inventors: Masanobu SHIRAKAWA, Tokumasa HARA
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Patent number: 11270765Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.Type: GrantFiled: January 21, 2021Date of Patent: March 8, 2022Assignee: Toshiba Memory CorporationInventors: Tokumasa Hara, Noboru Shibata
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Patent number: 11264090Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.Type: GrantFiled: September 8, 2020Date of Patent: March 1, 2022Assignee: Kioxia CorporationInventors: Tokumasa Hara, Noboru Shibata
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Patent number: 11238925Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.Type: GrantFiled: December 30, 2020Date of Patent: February 1, 2022Assignee: TOSHIBA MEMORY CORPORATIONInventors: Noboru Shibata, Tokumasa Hara
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Patent number: 11238924Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.Type: GrantFiled: September 10, 2020Date of Patent: February 1, 2022Assignee: Kioxia CorporationInventors: Tokumasa Hara, Noboru Shibata
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Patent number: 11226742Abstract: A memory device includes memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.Type: GrantFiled: May 26, 2020Date of Patent: January 18, 2022Assignee: KIOXIA CORPORATIONInventors: Masanobu Shirakawa, Tokumasa Hara
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Publication number: 20210350855Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: ApplicationFiled: July 21, 2021Publication date: November 11, 2021Applicant: Toshiba Memory CorporationInventors: Hiroshi SUKEGAWA, Ikuo MAGAKI, Tokumasa HARA, Shirou FUJITA
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Patent number: 11100999Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: GrantFiled: November 23, 2020Date of Patent: August 24, 2021Assignee: Toshiba Memory CorporationInventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
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Publication number: 20210166755Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.Type: ApplicationFiled: January 21, 2021Publication date: June 3, 2021Applicant: Toshiba Memory CorporationInventors: Tokumasa HARA, Noboru SHIBATA
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Publication number: 20210158867Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.Type: ApplicationFiled: September 10, 2020Publication date: May 27, 2021Applicant: Kioxia CorporationInventors: Tokumasa HARA, Noboru SHIBATA
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Publication number: 20210118495Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.Type: ApplicationFiled: December 30, 2020Publication date: April 22, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Noboru SHIBATA, Tokumasa HARA
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Publication number: 20210082497Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.Type: ApplicationFiled: September 8, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Tokumasa HARA, Noboru SHIBATA
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Publication number: 20210082524Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.Type: ApplicationFiled: November 25, 2020Publication date: March 18, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Takayuki AKAMINE, Masanobu SHIRAKAWA, Tokumasa HARA
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Publication number: 20210074363Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: ApplicationFiled: November 23, 2020Publication date: March 11, 2021Applicant: Toshiba Memory CorporationInventors: Hiroshi SUKEGAWA, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
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Patent number: 10937490Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.Type: GrantFiled: July 2, 2020Date of Patent: March 2, 2021Assignee: Toshiba Memory CorporationInventors: Tokumasa Hara, Noboru Shibata
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Patent number: 10916300Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit is received from an external controller, the received first data is written to the first memory cell. When second data including a second bit and a third bit is received from the controller after the first data is received, the first bit is read from the first memory cell and the 3-bit data is written to the first memory cell based on the read first bit and the received second data. In the 3-bit data written to the first memory cell, lower bit data is determined by three read operations, middle bit data is determined by two read operations, and upper bit data is determined by two read operations.Type: GrantFiled: June 9, 2020Date of Patent: February 9, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Noboru Shibata, Tokumasa Hara
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Patent number: 10885988Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.Type: GrantFiled: July 23, 2019Date of Patent: January 5, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takayuki Akamine, Masanobu Shirakawa, Tokumasa Hara