Abstract: A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correction code which is generated for the first data with a higher correction ability than that of the first error correction code. The first error correction unit performs error correction on the first data by using the first error correction code. The second error correction unit performs error correction on the first data by using the second error correction code. The interface transmits the first data after the error correction to a host.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of blocks. The blocks includes a first selection transistor, a second selection transistor, a plurality of memory cell transistors, a first selection gate line and a second selection gate line, and word lines. One of the blocks holds information on a word line, a first selection gate line and/or a second selection gate line including a short-circuiting defect.

Abstract: According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group.

Abstract: According to one embodiment, a semiconductor memory device includes memory cells and memory strings. When lower-page data is first written into a memory string, all memory cells corresponding to the lower-page data are made write-target, a program-verifying level of first ones of the write-targeted memory cells is a first threshold level, and a program-verifying level of second ones of the write-targeted memory cells is a second threshold level. The first threshold level corresponds to data associated with the lowest threshold level and is higher than a third threshold level. The second threshold level is higher than the first threshold level.

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes memory cells each storing 3 bits, a control unit that writes data to the non-volatile semiconductor memory, and an encoding unit that generates a first parity for user data stored in the first page, a second parity for user data stored in the second page, and a third parity for user data stored in the third page. The user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by a first data coding and a portion of the second parity and a portion of the third parity are written to the non-volatile semiconductor memory by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array having memory cells, word lines connected to the memory cell array, a generation circuit configured to generate voltages required for operations of the memory cell array, selection circuits connected to the word lines, respectively, each of the selection circuits being configured to select a voltage applied to a word line from the voltages, and a transfer unit configured to transfer items of control data for selecting the voltage to the selection circuits, respectively. The transfer unit includes transfer circuits which shift an enable signal in sequence. The transfer circuits include latch circuits which hold the items of control data based on the shifted enable signal, respectively.

Abstract: According to one embodiment, a memory controller that controls a non-volatile semiconductor memory including a memory cell of 3 bits/cell includes a controller that extracts bits which becomes an error caused by the movement to the adjacent threshold voltage distribution from a first bit and a second bit of data to be written in each of the memory cells to generate a virtual page and an encoding unit that generate an error correcting code for the virtual page and writes the data for three pages and the error correcting code in the non-volatile semiconductor memory.

Abstract: According to one embodiment, a semiconductor device includes a NAND flash memory, an input/output unit, a switch, and a controller. The input/output unit includes an ECC unit configured to perform an ECC process on data input to the NAND flash memory, and/or data output from the NAND flash memory, and an interface configured to exchange data with an external apparatus, and controls input/output of data between the NAND flash memory and the external apparatus. The switch is connected to the NAND flash memory and the input/output unit. The controller controls the NAND flash memory and the input/output unit, and switches a connection between the NAND flash memory and the ECC unit, and a connection between the NAND flash memory and the interface via the switch.

Abstract: A memory system includes a NAND flash memory having a page buffer capable of holding a page of data and a cell array having a plurality of pages. The system also includes a plurality of memory portions electrically connected to the NAND flash memory via a data bus, and a controller for controlling the NAND flash memory and the plurality of memory portions. A width of the data bus is less than a size of the page of data. When any one of a write operation and a read operation is performed on the NAND flash memory, the controller exchanges data held in the page buffer and data held in one memory portion of the plurality of memory portions.

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

Abstract: According to one embodiment, a semiconductor device includes a first sequencer and a second sequencer. The first sequencer operates at a first frequency. The second sequencer operates at a second frequency that is higher than the first frequency. In the first mode, the first sequencer operates in accordance with an instruction received from an external apparatus, and the second sequencer operates under control of the first sequencer. In the second mode, the second sequencer operates in accordance with an instruction received from the external apparatus, and the operation of the first sequencer is stopped.

Abstract: According to one embodiment, a semiconductor memory system includes a first semiconductor memory device, a second semiconductor memory device, and a wiring line. The wiring line is connected between the first semiconductor memory device and the second semiconductor memory device. When one of the first and second semiconductor memory devices discharges electric charge, the other of the first and second semiconductor memory devices receives the discharged electric charge through the wiring line.

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array having memory cells, word lines connected to the memory cell array, a generation circuit configured to generate voltages required for operations of the memory cell array, selection circuits connected to the word lines, respectively, each of the selection circuits being configured to select a voltage applied to a word line from the voltages, and a transfer unit configured to transfer items of control data for selecting the voltage to the selection circuits, respectively. The transfer unit includes transfer circuits which shift an enable signal in sequence. The transfer circuits include latch circuits which hold the items of control data based on the shifted enable signal, respectively.

Abstract: According to one embodiment, a memory system includes a nonvolatile first memory configured to store a boot program, a volatile second memory, a detection circuit configured to detect a level of a power supply voltage, and to generates an interrupt when the power supply voltage becomes less than a first level, and a state machine configured to execute a sequence including a first read operation for reading the boot program from the first memory and a transfer operation for transferring the read boot program to the second memory at power-on. The state machine includes a waiting state for waiting until the interrupt is deactivated when the interrupt is activated during the first read operation or the transfer operation.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory configured to receive a first clock and including a first buffer configured to perform a data input operation and a data output operation, a second memory including a second buffer configured to perform a data input operation and a data output operation, and a data bus configured to connect the first buffer and the second buffer. The first memory transfers a second clock to the second memory using the first clock. The first buffer transfers data to the second memory in response to the first clock. The second buffer receives the data from the first buffer in response to the second clock.

Abstract: A memory system includes a NAND flash memory having a page buffer capable of holding a page of data and a cell array having a plurality of pages. The system also includes a plurality of memory portions electrically connected to the NAND flash memory via a data bus, and a controller for controlling the NAND flash memory and the plurality of memory portions. A width of the data bus is less than a size of the page of data. When any one of a write operation and a read operation is performed on the NAND flash memory, the controller exchanges data held in the page buffer and data held in one memory portion of the plurality of memory portions.

Abstract: According to one embodiment, a semiconductor memory device includes a memory including an array of memory cells. A buffer comprises latches to hold data from the memory cells. The latches constitute latch groups. The latches of each latch group are connected to corresponding one common line through a transfer circuit. An error corrector is connected to the common lines and detects an error bit in received data. A data transfer controller causes the buffer to read out data from memory cells to be verified, repeats reading out of all data in the latches in one latch group to corresponding one of common lines as to-be-verified data segment for different latch groups, and transfers the to-be-verified data segments to the error corrector. A verify controller causes the error corrector to determine whether an error bit is included in to-be-verified data includes the to-be-verified data segments.

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.