Patents by Inventor Tokumasa Hara

Tokumasa Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY SYSTEM, MEMORY CONTROLLER AND MEMORY CONTROL METHOD
    Publication number: 20170075599
    Abstract: According to an embodiment, a memory system includes: a non-volatile memory; an encoding unit that generates a code word in which zero and one occur at different occurrence rates by encoding data; and a control unit that writes k third data items and fourth data items into the non-volatile memory. The k is an integer larger than or equal to zero and smaller than or equal to n. The n is an integer larger than or equal to two. The k third data items are obtained by encoding k second data items with the encoding unit among first data items including n second data items and having a first data length. The fourth data items are obtained by removing data corresponding to the k third data items from the first data items. The third data items are generated by encoding the second data items with encoders, respectively.
    Type: Application
    Filed: March 10, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Osamu TORII, Tokumasa HARA, Hironori UCHIKAWA
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20170060482
    Abstract: According to one embodiment, a controller executes a first data conversion for write data to be written into a first page. The first data conversion includes increasing a ratio of a number of a first value to a total number of pieces of data. The controller executes a second data conversion for write data to be written into a second page.
    Type: Application
    Filed: March 3, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tokumasa HARA, Kiichi TACHI, Susumu TAMON, Shigefumi IRIEDA
  • Memory system and control method
    Patent number: 9569355
    Abstract: According to an embodiment, a memory system includes multiple nonvolatile memories to/from each of which data can be written/read independently of one another; and a controller configured to control writing of data to and reading of data from the nonvolatile memories. Each of the nonvolatile memories includes a data storage including a normal data storage area for storing the data and a redundant data storage area for writing the data avoiding defect positions in the normal data storage area; and a defect information storage configured to store defect information indicating information on a defect of the data storage included in another nonvolatile memory different from the present nonvolatile memory.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yohei Hasegawa, Shigehiro Asano, Tokumasa Hara
  • MEMORY CONTROLLER AND SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20170039003
    Abstract: A memory controller includes: a host interface configured to receive a read command from the outside of the memory controller; and a read controller configured to perform a data read operation on a memory device according to the read command. The read controller performs a data read operation on a set of memory cells and determines a first and second values. The first value is a number of memory cells having a first threshold voltage among the set of memory cells, and the second value is a number of memory cells having a second threshold voltage among the set of memory cells. The read controller determines a first read voltage based on only the first and second values and performs a data read operation on the set of memory cells using the first read voltage.
    Type: Application
    Filed: March 2, 2016
    Publication date: February 9, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tokumasa Hara
  • Memory system and method of controlling nonvolatile memory
    Patent number: 9502129
    Abstract: According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: November 22, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Riki Suzuki, Toshikatsu Hida, Tokumasa Hara
  • SEMICONDUCTOR MEMORY DEVICE INCLUDING A CONTROL CIRCUIT AND AT LEAST TWO MEMORY CELL ARRAYS
    Publication number: 20160299692
    Abstract: A memory device includes memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.
    Type: Application
    Filed: June 16, 2016
    Publication date: October 13, 2016
    Inventors: Masanobu SHIRAKAWA, Tokumasa HARA
  • MEMORY SYSTEM
    Publication number: 20160266955
    Abstract: A memory system includes a memory and a controller. The memory includes a first memory chip and a second memory chip. The controller controls the memory. Each of the first and second memory chips includes string units and blocks including the string units. The memory holds information indicating a partial bad block including a bad string unit, and indicating which one of string units is the bad string unit in the partial bad block.
    Type: Application
    Filed: September 8, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naomi TAKEDA, Tokumasa HARA, Masanobu SHIRAKAWA, Hiroshi YAO
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20160259576
    Abstract: According to one embodiment, a nonvolatile memory system includes a memory including a first memory and a second memory, the first memory including memory strings, the memory strings including memory cell transistors connected in series; and a memory controller which compresses a failure string position information of the first memory, which stores the compressed failure string position information in the second memory, and which decompresses the compressed failure string position information stored in the second memory.
    Type: Application
    Filed: September 8, 2015
    Publication date: September 8, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shohei ASAMI, Tokumasa HARA, Hiroshi YAO, Kenichiro YOSHII, Riki SUZUKI, Toshikatsu HIDA, Osamu TORII
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    Publication number: 20160260483
    Abstract: A semiconductor memory device includes a block of memory cells including first, second, and third memory cells, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, a third word line electrically connected to a gate of the third memory cell, and a control circuit configured to access the block in one of at least first and second modes to perform an operation thereon. When the control circuit accesses the block in the first mode, the same voltage is applied to the first and second word lines throughout the operation, and when the control circuit accesses the block in the second mode, the same voltage is applied to the second and third word lines throughout the operation.
    Type: Application
    Filed: February 26, 2016
    Publication date: September 8, 2016
    Inventors: Toshifumi SHANO, Masanobu SHIRAKAWA, Tokumasa HARA
  • Semiconductor memory device including strings including memory cell transistors
    Patent number: 9431112
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: August 30, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • MEMORY SYSTEM, MEMORY CONTROLLER AND MEMORY CONTROL METHOD
    Publication number: 20160247581
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a memory interface, a storage unit which stores defective memory cell information, and a storage location control unit which creates second data of a second data length longer than a first data length based on an area at a write destination of first data of the first data length, causes the memory interface to write a plurality of second data to the nonvolatile memory, causes the memory interface to read the second data corresponding to the first data instructed to be read from the nonvolatile memory, and restores the first data based on the read second data and the defective memory cell information.
    Type: Application
    Filed: September 9, 2015
    Publication date: August 25, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Riki SUZUKI, Toshikatsu Hida, Tokumasa Hara, Kenichiro Yoshii, Youhei Kouchi, Norikazu Yoshida
  • MEMORY DEVICE AND METHOD OF READING DATA
    Publication number: 20160225457
    Abstract: A memory device of an embodiment includes a memory cell array and a controller. In the memory cell, data is written per page unit and is erased per block which is a multiple the page unit of a natural number of two or more. The block includes memory strings, each including memory cells capable of storing data of one or more bits with a threshold voltage indicative of an erase state in which data is erased and one or more threshold voltages which are higher than the voltage indicative of the erase state and indicate written states in which data is written. The controller selects one of adjustment values of positive and negative values based on data read from a first memory cell of the memory cells, and reads data from a second memory cell of the memory cells using the selected adjustment value and a first read voltage.
    Type: Application
    Filed: March 2, 2015
    Publication date: August 4, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tokumasa HARA, Hitoshi Iwai
  • Semiconductor memory device including a control circuit and at least two memory cell arrays
    Patent number: 9396775
    Abstract: A memory device includes first and second memory cell arrays, and a control circuit configured to output first information indicating whether the first memory cell array is in a ready state in which the control circuit is ready to receive a command to access the first memory cell array or a busy state in which the control circuit is not ready to receive the command to access the first memory cell array, and second information indicating whether the second memory cell array is in a ready state in which the control circuit is ready to receive a command to access the second memory cell array or a busy state in which the control circuit is not ready to receive the command to access the second memory cell array.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: July 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanobu Shirakawa, Tokumasa Hara
  • Semiconductor memory device
    Patent number: 9299438
    Abstract: According to one embodiment, a semiconductor memory device includes a first string; a second string; and a controller. The first string is coupled with a first bit line and includes first memory cells. The second string is coupled with a second bit line and includes second memory cells. The controller executes writing first data into the first memory cells and writing second data into the second memory cells simultaneously. The controller reads data from the first and second strings after writing the first and second data.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: March 29, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tokumasa Hara, Naoya Tokiwa, Hiroshi Sukegawa, Hitoshi Iwai, Toshifumi Shano, Shirou Fujita
  • METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20160077913
    Abstract: According to an embodiment, The control method includes reading a plurality of first pages in parallel on the basis of respectively different operation parameters. each of the first pages is respectively included in a plurality of first blocks. Each of the operation parameters includes a read voltage. The control method includes performing error correction on each of read data, and selecting one operation parameter out of the plurality of different operation parameters based on a result of the error correction.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 17, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi YAO, Hiroshi SUKEGAWA, Tokumasa HARA
  • MEMORY SYSTEM
    Publication number: 20160070471
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Application
    Filed: February 12, 2015
    Publication date: March 10, 2016
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NON-VOLATILE MEMORY
    Publication number: 20160049204
    Abstract: According to one embodiment, a controller groups a plurality of memory cells in each of the pages into a plurality of groups. The plurality of groups includes a first group and a second group. In a case of reading data from a first page, The controller performs first reading. The first reading includes reading data from the first page by using a first operation parameter for the first group. The controller performs second reading. The second reading includes reading data from the first page by using a second operation parameter for the second group. The controller merges first read data and second read data, and return the merged data as read data read from the first page. The first read data is acquired by the first reading. The second read data is acquired by the second reading.
    Type: Application
    Filed: March 3, 2015
    Publication date: February 18, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daiki WATANABE, Hiroshi Sukegawa, Hiroshi Yao, Tokumasa Hara, Naomi Takeda
  • Memory system and method of controlling nonvolatile memory
    Patent number: 9251892
    Abstract: According to an embodiment, a controller specifies a first voltage range that has a first distribution quantity, a second voltage range that is adjacent to a lower voltage side of the first voltage range, and a third voltage range that is adjacent to a higher voltage side of the first voltage range. The first distribution quantity is a minimum value of the memory cells. The controller determines a read voltage by using the first voltage range, a first representative voltage value in the first voltage range, the first distribution quantity, a second distribution quantity corresponding to the second voltage range, and a third distribution quantity corresponding to the third voltage range.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: February 2, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shohei Asami, Toshikatsu Hida, Tokumasa Hara, Riki Suzuki
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    Publication number: 20160012916
    Abstract: According to one embodiment, a semiconductor memory device includes: transistors; NAND strings; a bit line; a source line; and string sets. The transistors are stacked above a semiconductor substrate. In one of the string sets, a first transistor in a first NAND string has a first threshold, and a first transistor in a second NAND string has a second threshold lower than the first threshold.
    Type: Application
    Filed: September 10, 2014
    Publication date: January 14, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tokumasa HARA, Takuya HAGA
  • Nonvolatile memory and data writing method
    Patent number: 9230664
    Abstract: According to one embodiment, a nonvolatile memory includes a memory cell array having a plurality of memory cells configured to store 3-bit data corresponding to first to third pages. Data coding, in which first page data values have one boundary, and second and three page data values each have three boundaries, is used to perform a first stage program based on data written into first page d, a second stage program based on data written into the first, second, and third pages, and a third stage program based on data written into the first, second, and third pages.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: January 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tokumasa Hara, Noboru Shibata