Patents by Inventor Tokuo Kure
Tokuo Kure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9744569Abstract: A method for cleaning piping including the steps of supplying an acid to a cleaning water to prepare a cleaning water having pH of 4 or lower, mixing ozone gas to the cleaning water, and passing the cleaning water through the piping to be cleaned, or a cleaning system for piping, the system including a reservoir which retains cleaning water, an acid providing means supplies an acid to the cleaning water, an ozone generation means which generates ozone gas, a circulation flow path including a circulation pump which connects the reservoir and the ozone generation means in the form of a closed circuit, and circulates the cleaning water between the reservoir and ozone generation means, a conduction flow path including a conveying pump which communicates the reservoir and the piping to be cleaned, and conveys the cleaning water retained in the reservoir through the piping to be cleaned.Type: GrantFiled: October 18, 2013Date of Patent: August 29, 2017Assignee: HITACHI, LTD.Inventors: Takaaki Suematsu, Tokuo Kure, Kenji Saito, Eiji Higashi, Tomoyuki Araki
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Publication number: 20150298179Abstract: A method for cleaning piping including the steps of supplying an acid to a cleaning water to prepare a cleaning water having pH of 4 or lower, mixing ozone gas to the cleaning water, and passing the cleaning water through the piping to be cleaned, or a cleaning system for piping, the system including a reservoir which retains cleaning water, an acid providing means supplies an acid to the cleaning water, an ozone generation means which generates ozone gas, a circulation flow path including a circulation pump which connects the reservoir and the ozone generation means in the form of a closed circuit, and circulates the cleaning water between the reservoir and ozone generation means, a conduction flow path including a conveying pump which communicates the reservoir and the piping to be cleaned, and conveys the cleaning water retained in the reservoir through the piping to be cleaned.Type: ApplicationFiled: October 18, 2013Publication date: October 22, 2015Inventors: Takaaki SUEMATSU, Tokuo KURE, Kenji SAITO, Eiji HIGASHI, Tomoyuki ARAKI
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Patent number: 7259104Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.Type: GrantFiled: September 29, 2003Date of Patent: August 21, 2007Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Takafumi Tokunaga, Tadashi Umezawa, Motohiko Yoshigai, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takashi Sato, Yasushi Goto
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Publication number: 20060275986Abstract: A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.Type: ApplicationFiled: August 7, 2006Publication date: December 7, 2006Inventors: Takashi Kobayashi, Yasushi Goto, Tokuo Kure, Hideaki Kurata, Hitoshi Kume, Katsutaka Kimura, Syunichi Saeki
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Patent number: 7105409Abstract: A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.Type: GrantFiled: July 27, 2004Date of Patent: September 12, 2006Assignee: Renesas Technology Corp.Inventors: Takashi Kobayashi, Yasushi Goto, Tokuo Kure, Hideaki Kurata, Hitoshi Kume, Katsutaka Kimura, Syunichi Saeki
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Patent number: 7049243Abstract: A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.Type: GrantFiled: January 12, 2004Date of Patent: May 23, 2006Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Patent number: 6878586Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: GrantFiled: June 11, 2003Date of Patent: April 12, 2005Assignee: Renesas Technology Corp.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Patent number: 6849191Abstract: According to the present invention, there is provided a sample surface treating apparatus for processing a fine pattern by plasma etching, including a stage provided in a chamber, on which a sample to be subjected to a surface treatment is placed; etching gas supply source for continuously supplying an etching gas for plasma generation into the chamber; a plasma generator for generating a high-density plasma in the chamber; a bias power supply for applying a bias voltage of 100 kHz or higher to the stage independently of the plasma generation; and a pulse modulator for modulating the bias power supply at a frequency of 100 Hz to 10 kHz, wherein a surface treatment in which the minimum feature size is 1 ?m or smaller is performed on the sample placed on the stage.Type: GrantFiled: February 12, 1999Date of Patent: February 1, 2005Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Tatsumi Mizutani, Ryouji Hamasaki, Tokuo Kure, Takafumi Tokunaga, Masayuki Kojima
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Publication number: 20050014326Abstract: A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.Type: ApplicationFiled: July 27, 2004Publication date: January 20, 2005Inventors: Takashi Kobayashi, Yasushi Goto, Tokuo Kure, Hideaki Kurata, Hitoshi Kume, Katsutaka Kimura, Syunichi Saeki
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Publication number: 20040259361Abstract: A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.Type: ApplicationFiled: January 12, 2004Publication date: December 23, 2004Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Patent number: 6797566Abstract: A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed in first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.Type: GrantFiled: January 16, 2002Date of Patent: September 28, 2004Assignees: Renesas Technology Corp., Hitachi Device Engineering Corp. Ltd.Inventors: Takashi Kobayashi, Yasushi Goto, Tokuo Kure, Hideaki Kurata, Hitoshi Kume, Katsutaka Kimura, Syunichi Saeki
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Patent number: 6767838Abstract: A method and apparatus of treating a surface of a sample. A sample is arranged on a stage provided in a chamber, an etching gas is continuously supplied into the chamber and a plasma is generated from the etching gas. An rf bias at a frequency of 100 kHz or higher is applied to the stage independently of the generation of the plasma, and the rf bias is modulated at a frequency of 100 Hz to 10 kHz. Thereby, a surface treatment in which a minimum feature size is 1 &mgr;m or smaller is performed on the sample.Type: GrantFiled: October 19, 2000Date of Patent: July 27, 2004Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Tatsumi Mizutani, Ryouji Hamasaki, Tokuo Kure, Takafumi Tokunaga, Masayuki Kojima
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Publication number: 20040058541Abstract: To meet the requirements for ever smaller semiconductor devices, it is required to provide a sample surface processing method which is capable of processing a device of 1 micron or less, or more preferably 0.5 micron or less. It is also required to provide a surface processing method which allows a flat surface to be etched without irregularities occurring on the etched surface, and permits the multilayer film to be etched without underlying oxide film etched through.Type: ApplicationFiled: September 29, 2003Publication date: March 25, 2004Inventors: Tetsuo Ono, Takafuml Tokunaga, Tadashi Umezawa, Motohiko Yoshigai, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takashi Sato, Yasushi Goto
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Patent number: 6677244Abstract: A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.Type: GrantFiled: May 1, 2002Date of Patent: January 13, 2004Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Patent number: 6660647Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.Type: GrantFiled: January 11, 2001Date of Patent: December 9, 2003Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Takafumi Tokunaga, Tadashi Umezawa, Motohiko Yoshigai, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takashi Sato, Yasushi Goto
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Publication number: 20030205751Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: ApplicationFiled: June 11, 2003Publication date: November 6, 2003Applicant: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Publication number: 20030132198Abstract: According to the present invention, there is provided a sample surface treating apparatus for processing a fine pattern by plasma etching, comprising: a stage provided in a chamber, on which a sample to be subjected to a surface treatment is placed; etching gas supplying means for continuously supplying an etching gas for plasma generation into the chamber; plasma generating means for generating a high-density plasma in the chamber; a bias power supply for applying a bias voltage of 100 kHz or higher to the stage independently of the plasma generation; and pulse modulating means for modulating the bias power supply at a frequency of 100 Hz to 10 kHz, wherein a surface treatment in which the minimum feature size is 1 &mgr;m or smaller is performed to the sample placed on the stand.Type: ApplicationFiled: February 12, 1999Publication date: July 17, 2003Inventors: TETSUO ONO, TATSUMI MIZUTANI, RYOUJI KAMASAKI, TOKUO KURE, TAKAFUMI TOKUNAGA, MASAYUKI KOJIMA
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Patent number: 6525336Abstract: A superfine electronic device is disclosed, which is constructed by atomic fine lines having a structure in which a plurality of atoms are arranged on one or a plurality of straight lines, in a ring shape or on curves with a size of atomic level, and which includes elements for doping electrons and holes. Using these atomic fine lines, it is possible to integrate semiconductor elements utilizing pn junctions at an atomic level with a high density. A groove having a sufficiently small size is formed in an insulating film disposed on a substrate. Then, atoms or molecules are supplied on the substrate and in the groove, which and are heated to a temperature sufficiently high for moving the atoms or molecules during or after the supply thereof to form a quantum fine line at edge portions of the groove.Type: GrantFiled: June 5, 1995Date of Patent: February 25, 2003Assignee: Hitachi, Ltd.Inventors: Seiichi Kondo, Yasuo Wada, Tsuyoshi Uda, Tokuo Kure, Tsuneo Ichiguchi, Shinji Okazaki, Yoshimasa Murayama
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Patent number: 6492277Abstract: Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.Type: GrantFiled: September 10, 1999Date of Patent: December 10, 2002Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Patent number: RE38296Abstract: A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.Type: GrantFiled: March 23, 1995Date of Patent: November 4, 2003Assignee: Hitachi, Ltd.Inventors: Noboru Moriuchi, Yoshiki Yamaguchi, Toshihiko Tanaka, Norio Hasegawa, Yoshifumi Kawamoto, Shin-ichiro Kimura, Toru Kaga, Tokuo Kure