Abstract: There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.

Abstract: A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.

Abstract: Before a high permittivity interlayer insulating film of a non-volatile memory having a two-level gate electrode structure, a surface of a substrate in a peripheral circuit MOS area is successively covered with a thermal oxide film and a polycrystalline silicon film. Before the interlayer insulating film is selectively removed on the peripheral circuit MOS area, the surface of the interlayer insulating film of the non-volatile memory is covered with a polycrystalline silicon film. When the interlayer insulating film in the peripheral circuit MOS area is removed, the polycrystalline silicon film as a lower layer in the peripheral circuit area serves as a buffer layer against contamination or damage due to the etching, and the conductive layer on the surface of the interlayer insulating film in the non-volatile memory portion also serves as a buffer layer against the contamination or damage due to the etching.

Abstract: A vertical semiconductor memory device is provided which capable of miniaturization. More particularly, a memory cell is provided having a trench capacitor and a vertical transistor in a dynamic random access memory suitable for high density integration. An object of this arrangement is to provide a vertical memory cell capable of miniaturization for use in a ultra-high density integration DRAM of a Gbit class. This memory cell is characterized in that each memory cell is covered with an oxide film, an impurity area does not exist on the substrate side, an area in which a channel area is formed is a hollow cylindrical single crystal area, connection of impurity areas as source-drain areas and bit lines and the electrode of a capacitor is made by self-alignment and connection between a word line electrode and a gate electrode is also made by self-alignment.

Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.

Abstract: A semiconductor device and the method of manufacturing the same are disclosed, the semiconductor device having a plurality of elements isolated by a groove having a gentle slope at the upper side wall, and a steep slope at the lower side wall. This groove provides low steps on its mouth and occupies a small area on the substrate, thus enabling an extremely high-density integrated circuit to be formed.

Abstract: Disclosed is a semiconductor device including a charge storage capacitor having a storage electrode which is electrically connected to a switching transistor through a contact hole provided in an insulator and which has a greater film thickness than the radius of the contact hole, at least a part of the storage electrode being disposed above a data line. It is possible to reduce the memory cell area while preventing lowering in the capacitance, and thus realize high density and high integration of semiconductor devices.

Abstract: A method of manufacturing a bipolar transistor semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.

Abstract: Herein disclosed is a semiconductor device of high density. The semiconductor device having a high density and a microstructure is required to have a high breakdown voltage and a high speed even with a low supply voltage. The semiconductor device comprises: a semiconductor body; a gate insulating film formed over the body; and a MOS transistor having a source/drain region formed in the body and a gate electrode film formed over the gate insulating film. The gate electrode film is composed of two or more films having different etching rates. The gate etching is stopped at the interface of the composite film to form an inverse-T gate electrode structure; and in that an electric conduction is observed between the component films. Thus, the overlap between the gate and the drain can be controlled.

Abstract: A semiconductor memory is provided having a capacitor formed by utilizing a groove formed in a semiconductor substrate and an insulated gate field effect transistor. In particular, an arrangement is provided to prevent a depletion region formed around the groove from growing into an adjacent capacitor. By virtue of this, both the area occupied by each memory cell and the distance between the memory cells can be made very small. Accordingly, high density integration is facilitated.

Abstract: A dry etching method including the steps of introducing etching and deposition gases alternately into a reaction chamber at predetermined time intervals, etching the exposed surface of an article to be etched and applying deposition to the surface film thereof alternately by making plasma generated by applying power to the etching and deposition gases introduced into the reaction chamber come in contact with the article to be etched in the reaction chamber in order to etch the surface, is characterized in that the power is applied after the passage of predetermined time from the start of the introduction of the deposition gas and before the etching gas is introduced and cut off when the introduction of the etching gas is suspended.

Abstract: The side wall part of a recess dug in a Si substrate is used as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a desired capacitor capacitance can be attained without increasing the breakdown of an insulator film ascribable to the conventional approach of thinning of the insulator film. In addition, a vertical switching transistor is formed on the Si substrate, whereby the Si substrate can be entirely utilized for the formation of the capacitor.

Abstract: Polycrystalline silicon which is provided within a trench for isolating a plurality of bipolar transistors from each other is electrically connected to the collector of one of the bipolar transistor. Since the trench for isolation can also be used to lead out the collector electrode, the required area is minimized. Thus, the arrangement is effective in creasing the integration density.

Abstract: A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.

Abstract: A semiconductor memory device having STC cells wherein major portions of active regions consisting of channel-forming portions are tilted at an angle of 45.degree. with respect to the word lines and the bit lines that meet at right angles with each other, enabling the storage capacity portions to be arranged very densely and sufficiently large capacities to be maintained with very small cell areas. In the semiconductor memory device, furthermore, the storage capacity portions are formed even on the bit lines. Therefore, the bit lines are shielded, the capacitance between the bit lines decreases, and the memory array noise decreases.

Abstract: The side wall part of a recess dug in a Si substrate is used as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a desired capacitor capacitance can be attained without increasing the breakdown of an insulator film ascribable to the conventional approach of thinning of the insulator film. In addition, a vertical switching transistor is formed on the Si substrate, whereby the Si substrate can be entirely utilized for the formation of the capacitor.

Abstract: A semiconductor device is disclosed, which includes bipolar transistor each having an emitter, base and collector formed inside each protruding portion of a semiconductor substrate, and trenches for device isolation. The bipolar transistor and the trench are spaced apart from each other by a predetermined spacing. According to this arrangement, the width of a base contact becomes uniform and any change of transistor characteristics can be prevented effectively.