Patents by Inventor Tokuo Kure

Tokuo Kure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4901128
    Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.
    Type: Grant
    Filed: November 24, 1986
    Date of Patent: February 13, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Tokuo Kure, Masanobu Miyao, Yoshifumi Kawamoto, Katsuhiro Shimohigashi, Yoshio Sakai, Osamu Minato, Toshiaki Masuhara, Mitsumasa Koyanagi, Shinji Shimizu
  • Patent number: 4882289
    Abstract: A semiconductor memory wherein a memory cell region having a plurality of memory cells and has higher altitude from the surface of semiconductor substrate is formed in the recessed part of semiconductor substrate having the recessed part and projected part and a peripheral circuit region which is comparatively low from the surface of semiconductor substrate is formed to the projected part of semiconductor substrate.
    Type: Grant
    Filed: April 22, 1988
    Date of Patent: November 21, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Moriuchi, Yoshiki Yamaguchi, Toshihiko Tanaka, Norio Hasegawa, Yoshifumi Kawamoto, Shin-ichiro Kimura, Toru Kaga, Tokuo Kure
  • Patent number: 4873203
    Abstract: An insulation film on silicon buried in a trench is prepared by forming a field oxide film by using a first Si.sub.3 N.sub.4 mask formed on a silicon substrate, forming a second Si.sub.3 N.sub.4 mask for formation of a trench, forming a trench in the silicon substrate by using the second Si.sub.3 N.sub.4 mask, burying polycrystalline silicon in the trench, removing the second Si.sub.3 N.sub.4 mask while leaving the first Si.sub.3 N.sub.4 mask and oxidizing the surface of the polycrystalline silicon buried in the trench by thermal oxidation. The so-formed insulation film on silicon buried in the trench has a uniform thickness and a high dielectric strength. The surface of the substrate at a part where an active element will be formed in the future is not oxidized.
    Type: Grant
    Filed: July 19, 1988
    Date of Patent: October 10, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Toru Kaga, Shinichiro Kimura, Tokuo Kure, Yoshifumi Kawamoto, Hideo Sunami
  • Patent number: 4860071
    Abstract: A memory is disclosed which uses a microcapacitor as a data storage portion. The microcapacitor uses as its main electrode surface the side wall of a first trench formed on a semiconductor substrate, and is fabricated by diffusing an impurity from a second diffusion trench adjacent to the first trench by setting the shapes and diffusion conditions of the first and second trenches so that the tip of the diffusion layer reaches the side wall of the first trench. The capacitor uses the diffusion layer as one of the electrodes. An insulating film is deposited on the side wall of the first trench and an electrode as the other electrode of the capacitor is deposited on this insulating film. The memory can reduce a leakage current between memory cells by connecting the capacitor to a transistor fabricated in the same semiconductor substrate, and can be formed within a limited space.
    Type: Grant
    Filed: February 10, 1988
    Date of Patent: August 22, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Tokuo Kure, Atsushi Hiraiwa, Yasuo Wada
  • Patent number: 4829361
    Abstract: A semiconductor device wherein a layer doped with impurities is provided between a buried layer and an epitaxial layer, said layer doped with impurities having a conductivity of the type opposite to that of said buried layer and said epitaxial layer, a reversely biasing voltage is applied across the buried layer and the layer doped with impurities, and side surfaces of the epitaxial layer are surrounded by an insulator.This helps effectively prevent the element formed in the epitaxial layer from being affected by .alpha.-particles and greatly improve reliability of the semiconductor device.
    Type: Grant
    Filed: November 16, 1987
    Date of Patent: May 9, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiko Sagara, Tohru Nakamura, Kazuo Nakazato, Tokuo Kure, Kiyoji Ikeda, Noriyuki Homma
  • Patent number: 4825281
    Abstract: A semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.
    Type: Grant
    Filed: October 21, 1982
    Date of Patent: April 25, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Tohru Nakamura, Masatoshi Matsuda, Takao Miyazaki, Tokuo Kure, Takahiro Okabe, Minoru Nagata
  • Patent number: 4812894
    Abstract: A semiconductor device includes a first insulation film formed on a monocrystalline substrate and having an opening, a monocrystalline semiconductor layer formed so as to protrude into the first insulation film, and a conductive layer formed in contact with the side section of the monocrystalline semiconductor layer and extending over a second insulation film formed on the monocrystalline semiconductor layer.
    Type: Grant
    Filed: May 3, 1988
    Date of Patent: March 14, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Tohru Nakamura, Kazuo Nakazato, Noriyuki Homma, Kazuhiko Sagara, Takeo Shiba, Tokuo Kure, Tetsuya Hayashida
  • Patent number: 4751557
    Abstract: A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.
    Type: Grant
    Filed: September 8, 1986
    Date of Patent: June 14, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Tokuo Kure, Yoshifumi Kawamoto, Masao Tamura, Masanobu Miyao
  • Patent number: 4635090
    Abstract: A semiconductor device and the method of manufacturing the same are disclosed, the semiconductor device having a plurality of elements isolated by a groove having a gentle slope at the upper side wall, and a steep slope at the lower side wall. This groove provides low steps on its mouth and occupies a small area on the substrate, thus enabling an extremely high-density integrated circuit to be formed.
    Type: Grant
    Filed: May 13, 1985
    Date of Patent: January 6, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Tokuo Kure, Akira Sato, Hisayuki Higuchi
  • Patent number: 4529476
    Abstract: A dry-etching gas suitable for selective etching of silicon nitride and a process for selectively dry-etching silicon nitride with the dry-etching gas are disclosed. Silicon nitride can be dry-etched with a higher selectivity or at a higher etching rate than silicon dioxide and silicon, and a process for fabricating semi-conductor devices can be simplified and devices with a novel structure can be realized.
    Type: Grant
    Filed: June 1, 1984
    Date of Patent: July 16, 1985
    Assignees: Showa Denko K.K., Hitachi, Ltd.
    Inventors: Yoshifumi Kawamoto, Hiroshi Kawakami, Tokuo Kure, Shinichi Tachi, Norikazu Hashimoto, Tsuyoshi Takaichi
  • Patent number: 4396460
    Abstract: After filling grooves with a filling material, this filling material is etched by the use of a double-layer film which is made of substances different from each other.The side etching of the lower film of the double-layer film and the etching of the filling material are alternately performed in such a manner that each etching is carried out a plurality of number of times. Thus, the upper surface of the filling material contained in each groove can be flattened.
    Type: Grant
    Filed: May 21, 1982
    Date of Patent: August 2, 1983
    Assignee: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Tokuo Kure, Takeo Shiba, Hisayuki Higuchi