Abstract: An imaging system may include an image sensor having an array of dual gain pixels. Each pixel may be operated using an improved three read method and an improved four read method such that all signals are read in a high gain configuration in order to prevent electrical offset in signal levels. Each pixel may be operated using an improved three read, two analog to digital conversion (ADC) method in which a frame buffer is used to store calibration data. Each pixel may be operated using an improved three read, three ADC method in which no frame buffer is required. A high dynamic range image signal may be produced for each pixel based on signals read from the pixel and on light conditions.

Abstract: An imaging pixel may be provided with a photodiode and a floating diffusion region. The pixel may include multiple charge storage regions interposed between the photodiode and the floating diffusion region. A first charge storage region may be used to store charge from the photodiode for global shutter functionality. A second charge storage region may not be coupled to the photodiode. The second charge storage region may be used to determine how much charge is generated in the charge storage region from incident light on the charge storage region. The second charge storage region may help account for incident light noise in the first charge storage region. The second charge storage region may be the same size as the first charge storage region, or may be smaller than the first charge storage region.

Abstract: In accordance with an embodiment, a pixel includes a first stage coupled to a second stage. The second stage includes a sampling capacitor and a subtraction capacitor.

Abstract: In accordance with an embodiment, a pixel includes a first stage coupled to a second stage. The second stage includes a sampling capacitor and a subtraction capacitor.

Abstract: In accordance with an embodiment of the present invention, an image sensor comprises a plurality of pixel sensing circuits. Each pixel sensing circuit includes a photodiode and a storage node. Each pixel sensing circuit further includes a first transistor coupled between the photodiode and the storage node and a second transistor coupled between the photodiode and a shared node. The shared node is coupled to the plurality of pixel sensing circuits. The image sensor may include a reset transistor and/or a read-out circuit coupled to the shared node.

Abstract: An analog-to-digital converter (ADC) architecture to implement a non-linear flash ADC. The apparatus includes a non-linear resistor, a non-linear comparator, and an inverse non-linear encoder. The non-linear resistor has an input and a plurality of non-linear voltage outputs. The non-linear comparator ladder is coupled to the plurality of non-linear voltage outputs of the non-linear resistor. The non-linear comparator ladder includes a bank of comparators to compare an input signal to each of a plurality of non-linear voltage signals corresponding to the plurality of non-linear voltage outputs. The inverse non-linear encoder is coupled to the non-linear comparator ladder. The inverse non-linear encoder generates a digital output code based on the input signal and the plurality of non-linear voltage signals.