Patents by Inventor Tomohide Terashima
Tomohide Terashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11670634Abstract: There are provided a transistor including a first semiconductor layer of a first conductivity type, a second semiconductor layer thereabove, a first impurity region of a second conductivity type provided in an upper layer part of the second semiconductor layer, a second impurity region of a first conductivity type provided in an upper layer part of the first impurity region, a gate electrode facing the first impurity region and the second semiconductor layer with a gate insulating film interposed in between, and first and second main electrodes; a parasitic transistor with the second impurity region as a collector, the first and the second semiconductor layers as an emitter, and the first impurity region as a base; a parasitic diode with the first impurity region as an anode, and the first and the second semiconductor layers as a cathode; and a pn junction diode with the first impurity region as an anode, and the second impurity region as a cathode.Type: GrantFiled: January 7, 2020Date of Patent: June 6, 2023Assignee: Mitsubishi Electric CorporationInventor: Tomohide Terashima
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Patent number: 11552073Abstract: A semiconductor device includes a main IGBT, a sense, a resistor, a MOSFET and a diode, as main components. The sense IGBT and the main IGBT are connected in parallel with each other. The drain of MOSFET is connected to the gate of the sense IGBT, the source thereof is connected to the gate of the main IGBT, and the gate thereof is connected to the emitter of the sense IGBT and the cathode of diode. One end of the resistor is connected to the gate of the main IGBT and the source of the MOSFET, and the other end of the resistor is connected to the emitter of the main IGBT and the anode of the diode.Type: GrantFiled: November 4, 2021Date of Patent: January 10, 2023Assignee: Mitsubishi Electric CorporationInventors: Sho Tanaka, Tomohide Terashima
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Publication number: 20220246603Abstract: A semiconductor device includes a main IGBT, a sense, a resistor, a MOSFET and a diode, as main components. The sense IGBT and the main IGBT are connected in parallel with each other. The drain of MOSFET is connected to the gate of the sense IGBT, the source thereof is connected to the gate of the main IGBT, and the gate thereof is connected to the emitter of the sense IGBT and the cathode of diode. One end of the resistor is connected to the gate of the main IGBT and the source of the MOSFET, and the other end of the resistor is connected to the emitter of the main IGBT and the anode of the diode.Type: ApplicationFiled: November 4, 2021Publication date: August 4, 2022Applicant: Mitsubishi Electric CorporationInventors: Sho TANAKA, Tomohide TERASHIMA
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Patent number: 11217449Abstract: There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.Type: GrantFiled: September 30, 2019Date of Patent: January 4, 2022Assignee: Mitsubishi Electric CorporationInventors: Tomohide Terashima, Yasuhiro Kagawa, Kensuke Taguchi
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Patent number: 11183386Abstract: There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.Type: GrantFiled: September 30, 2019Date of Patent: November 23, 2021Assignee: Mitsubishi Electric CorporationInventors: Tomohide Terashima, Yasuhiro Kagawa, Kensuke Taguchi
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Publication number: 20200335496Abstract: There are provided a transistor including a first semiconductor layer of a first conductivity type, a second semiconductor layer thereabove, a first impurity region of a second conductivity type provided in an upper layer part of the second semiconductor layer, a second impurity region of a first conductivity type provided in an upper layer part of the first impurity region, a gate electrode facing the first impurity region and the second semiconductor layer with a gate insulating film interposed in between, and first and second main electrodes; a parasitic transistor with the second impurity region as a collector, the first and the second semiconductor layers as an emitter, and the first impurity region as a base; a parasitic diode with the first impurity region as an anode, and the first and the second semiconductor layers as a cathode; and a pn junction diode with the first impurity region as an anode, and the second impurity region as a cathode.Type: ApplicationFiled: January 7, 2020Publication date: October 22, 2020Applicant: Mitsubishi Electric CorporationInventor: Tomohide TERASHIMA
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Publication number: 20200203166Abstract: There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.Type: ApplicationFiled: September 30, 2019Publication date: June 25, 2020Applicant: Mitsubishi Electric CorporationInventors: Tomohide TERASHIMA, Yasuhiro KAGAWA, Kensuke TAGUCHI
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Patent number: 9159563Abstract: A semiconductor device manufacturing method according to the present invention includes a step of arranging a plurality of processing objects on a first tray and a second tray adjacent to the first tray, a plurality of application steps in which application of an application substance to the plurality of processing objects is repeated a certain number of times by emitting the application substance from an application device formed right above a contact position at which the first tray and the second tray contact each other, by swinging the application device along a first direction across the contact position, and by moving the first tray and the second tray in a second direction perpendicular to the first direction, and an interchange step of interchanging the first tray and the second tray in position without changing the directions of the first tray and the second tray corresponding to the second direction, the interchange step being executed at least one time among the plurality of application steps.Type: GrantFiled: September 26, 2012Date of Patent: October 13, 2015Assignee: Mitsubishi Electric CorporationInventors: Tomohide Terashima, Yasuhiro Yoshiura, Eiko Otsuki
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Publication number: 20150228488Abstract: A semiconductor device manufacturing method according to the present invention includes a step of arranging a plurality of processing objects on a first tray and a second tray adjacent to the first tray, a plurality of application steps in which application of an application substance to the plurality of processing objects is repeated a certain number of times by emitting the application substance from an application device formed right above a contact position at which the first tray and the second tray contact each other, by swinging the application device along a first direction across the contact position, and by moving the first tray and the second tray in a second direction perpendicular to the first direction, and an interchange step of interchanging the first tray and the second tray in position without changing the directions of the first tray and the second tray corresponding to the second direction, the interchange step being executed at least one time among the plurality of application steps.Type: ApplicationFiled: September 26, 2012Publication date: August 13, 2015Applicant: Mitsubishi Electric CorporationInventors: Tomohide Terashima, Yasuhiro Yoshiura, Eiko Otsuki
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Patent number: 9048111Abstract: A semiconductor device includes a substrate, a buried insulating film formed on the substrate, an SOI layer formed on the buried insulating film, an insulating film formed to extend from a top surface of the SOI layer to the buried insulating film and to divide the SOI layer into a first SOI layer and a second SOI layer isolated from the first SOI layer, an element formed in the first SOI layer, and an electrode having at one end thereof a pad located directly above the second SOI layer, the other end of the electrode being connected to the first SOI layer. A cavity region is formed between the buried insulating film and the substrate directly below the first SOI layer. The portion of the buried insulating film directly below the second SOI layer is at least partially in direct contact with the substrate.Type: GrantFiled: April 15, 2014Date of Patent: June 2, 2015Assignee: Mitsubishi Electric CorporationInventors: Junichi Yamashita, Tomohide Terashima
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Publication number: 20150008557Abstract: A semiconductor device includes a substrate, a buried insulating film formed on the substrate, an SOI layer formed on the buried insulating film, an insulating film formed to extend from a top surface of the SOI layer to the buried insulating film and to divide the SOI layer into a first SOI layer and a second SOI layer isolated from the first SOI layer, an element formed in the first SOI layer, and an electrode having at one end thereof a pad located directly above the second SOI layer, the other end of the electrode being connected to the first SOI layer. A cavity region is formed between the buried insulating film and the substrate directly below the first SOI layer. The portion of the buried insulating film directly below the second SOI layer is at least partially in direct contact with the substrate.Type: ApplicationFiled: April 15, 2014Publication date: January 8, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Junichi YAMASHITA, Tomohide TERASHIMA
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Patent number: 8878239Abstract: On a main surface of a semiconductor substrate, an N? semiconductor layer is formed with a dielectric portion including relatively thin and thick portions interposed therebetween. In a predetermined region of the N? semiconductor layer, an N-type impurity region and a P-type impurity region are formed. A gate electrode is formed on a surface of a portion of the P-type impurity region located between the N-type impurity region and the N? semiconductor layer. In a predetermined region of the N? semiconductor layer located at a distance from the P-type impurity region, another P-type impurity region is formed. As a depletion layer block portion, another N-type impurity region higher in impurity concentration than the N? semiconductor layer is formed from the surface of the N? semiconductor layer to the dielectric portion.Type: GrantFiled: May 3, 2013Date of Patent: November 4, 2014Assignee: Mitsubishi Electric CorporationInventor: Tomohide Terashima
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Patent number: 8772903Abstract: A semiconductor device includes a plurality of floating regions, an insulating layer and a capacitance forming portion. The plurality of floating regions are arranged on a surface of a semiconductor substrate in a row, wherein the plurality of floating regions are provided with insulating regions therebetween. The plurality of floating regions include a first floating region and a second floating region. The second floating region is located farther than the first floating region from an island region of a predetermined potential on the semiconductor substrate. The insulating layer is interposed between each of the plurality of floating regions and a semiconductor material layer of the semiconductor substrate. The capacitance forming portion forms an external capacitance in parallel with the capacitance of the insulating region between the first floating region and the island region of the predetermined potential.Type: GrantFiled: July 13, 2011Date of Patent: July 8, 2014Assignee: Mitsubishi Electric CorporationInventor: Tomohide Terashima
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Patent number: 8710617Abstract: In a region located between a collector electrode and a semiconductor substrate, there are a portion where a hollow region is located and a portion where no hollow region is located. Between the collector electrode and the portion where no hollow region is located in the semiconductor substrate, a floating silicon layer electrically isolated by insulating films is formed.Type: GrantFiled: March 13, 2013Date of Patent: April 29, 2014Assignee: Mitsubishi Electric CorporationInventors: Junichi Yamashita, Tomohide Terashima
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Patent number: 8674471Abstract: A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.Type: GrantFiled: August 28, 2012Date of Patent: March 18, 2014Assignee: Mitsubishi Electric CorporationInventor: Tomohide Terashima
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Publication number: 20140015004Abstract: On a main surface of a semiconductor substrate, an N? semiconductor layer is formed with a dielectric portion including relatively thin and thick portions interposed therebetween. In a predetermined region of the N? semiconductor layer, an N-type impurity region and a P-type impurity region are formed. A gate electrode is formed on a surface of a portion of the P-type impurity region located between the N-type impurity region and the N? semiconductor layer. In a predetermined region of the N? semiconductor layer located at a distance from the P-type impurity region, another P-type impurity region is formed. As a depletion layer block portion, another N-type impurity region higher in impurity concentration than the N? semiconductor layer is formed from the surface of the N? semiconductor layer to the dielectric portion.Type: ApplicationFiled: May 3, 2013Publication date: January 16, 2014Applicant: Mitsubishi Electric CorporationInventor: Tomohide TERASHIMA
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Publication number: 20130292740Abstract: In a region located between a collector electrode and a semiconductor substrate, there are a portion where a hollow region is located and a portion where no hollow region is located. Between the collector electrode and the portion where no hollow region is located in the semiconductor substrate, a floating silicon layer electrically isolated by insulating films is formed.Type: ApplicationFiled: March 13, 2013Publication date: November 7, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Junichi YAMASHITA, Tomohide TERASHIMA
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Patent number: 8466515Abstract: On a main surface of a semiconductor substrate, an N? semiconductor layer is formed with a dielectric portion including relatively thin and thick portions interposed therebetween. In a predetermined region of the N? semiconductor layer, an N-type impurity region and a P-type impurity region are formed. A gate electrode is formed on a surface of a portion of the P-type impurity region located between the N-type impurity region and the N? semiconductor layer. In a predetermined region of the N? semiconductor layer located at a distance from the P-type impurity region, another P-type impurity region is formed. As a depletion layer block portion, another N-type impurity region higher in impurity concentration than the N? semiconductor layer is formed from the surface of the N? semiconductor layer to the dielectric portion.Type: GrantFiled: April 20, 2011Date of Patent: June 18, 2013Assignee: Mitsubishi Electric CorporationInventor: Tomohide Terashima
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Patent number: 8395231Abstract: A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.Type: GrantFiled: July 31, 2007Date of Patent: March 12, 2013Assignee: Mitsubishi Electric CorporationInventor: Tomohide Terashima
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Publication number: 20120319739Abstract: A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.Type: ApplicationFiled: August 28, 2012Publication date: December 20, 2012Applicant: Mitsubishi Electric CorporationInventor: Tomohide TERASHIMA